User Manual

12 Specification Update
HSH6 IIO CSR Lnkcon2 Field Selectable_De_Emphasis Cannot Be Set For
DMI2 Mode
Problem: The CSR lnkcon2 (Bus 0; Device 0; Function 0, Offset 0x1C0) field
selectable_de_emphasis (bit 6) cannot be set for a link in DMI2 Mode when the DMI
port is operating at 5 GT/s. The documentation has the attribute of RW-O (read, write
once), but the processor incorrectly operates as read-only.
Implication: When the link is in DMI2 mode, the de-emphasis cannot be changed for an upstream
component.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH7 PCIe* Receiver May Not Meet the Specification for AC Common Mode
Voltage And Jitter
Problem: Due to this erratum, PCIe receivers may not meet the specification for AC common
mode voltage (300 mV) and jitter (78.1 ps) at high temperatures when operating at 5
GT/s.
Implication: Specifications for PCIe receiver AC common mode voltage and jitter may not be met.
Intel has not observed this erratum on any commercially available system with any
commercially available PCIe devices.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH8 Receiver Termination Impedance On PCIe* 3.0 Does Not Comply With
The Specification
Problem: The PCIe* Base Specification revision 3.0 defines ZRX-HIGH-IMP-DC-NEG and ZRX-
HIGH-IMP-DC-POS for termination impedance of the receiver. The specified impedance
for a negative voltage (-150 mV to 0V) is expected to be greater than 1 Kohm.
Sampled measurements of this impedance as low as 400 ohms have been seen. The
specified impedance for a positive voltage (> 200 mV) is greater than 20 Kohms.
Sampled measurements of this impedance as low as 14.6 Kohms have been seen.
Implication: Intel has not observed functional failures from this erratum on any commercially
available platforms using any commercially available PCIe device.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH9 USB3 xHCI Not compatible with MSIs
Problem: When the PCH xHCI (Extensible Host Controller Interface) is configured to use MSI
interrupts, a PCIe device number conflict between the processor and xHCI controller
may cause the interrupts be routed incorrectly.
Implication: Due to this erratum, unpredictable system behavior may result.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH10 Writing R3QPI Performance Monitor Registers May Fail
Problem: Due to this erratum, attempting to write R3QPI performance monitor registers (Bus 0;
Device 11; Functions 1,2,5,6; Offset 0xA0-0xF7) may be unsuccessful.
Implication: A failed write to one or more R3QPI performance monitor registers is likely to yield
incorrect performance events counts.
Workaround: Consecutively write the identified registers twice with the same value before
performance monitoring is globally enabled.
Status: For the affected steppings, see the Summary Tables of Changes.