User Manual

Specification Update 11
Errata
HSH1 Intel® QPI Layer May Report Spurious Correctable Errors
Problem: Intel QPI may report an inband reset with no width change (error 0x22) correctable
error upon exit from the L1 power state as logged in its IA32_MC{5, 20, 21}_STATUS
MSRs (415H,451H,455H).
Implication: An unexpected inband reset with no width change error may be logged.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH2 NTB May Incorrectly Set MSI or MSI-X Interrupt Pending Bits
Problem: The NTB (Non-transparent Bridge) may incorrectly set MSI (Message Signaled
Interrupt) pending bits in MSIPENDING (BAR PB01BASE,SB01BASE; Offset 74H) while
operating in MSI-X mode or set MSI-X pending bits in PMSIXPBA (BAR PB01BASE,
SB01BASE; Offset 03000H) while operating in MSI mode.
Implication: Due to this erratum, NTB incorrectly sets MSI or MSI-X pending bits. The correct
pending bits are also set and it is safe to ignore the incorrectly set bits.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH3 Memory Controller May Incorrectly Issue a Refresh Command
Immediately After a Precharge Command
Problem: In PPD (Precharge Power Down) mode, the memory controller may incorrectly issue a
REF (refresh) command one cycle after a PREA (precharge) command, violating JEDEC
specifications.
Implication: Memory contents may be affected in precharge Power Down mode leading to
unpredictable system behavior.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum
Status: For the affected steppings, see the Summary Tables of Changes.
HSH4 Processor May Issue Unexpected NAK DLLP Upon PCIe* L1 Exit
Problem: Upon exiting the L1 link power state, the processor’s PCIe port may unexpectedly issue
a NAK DLLP (Data Link Layer Packet).
Implication: PCIe endpoints may unexpectedly receive and log a NAK DLLP.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH5 PECI DDR DIMM Digital Thermal Reading Returns Incorrect Value
Problem: When using the PECI RdPkgConfig() command to read PCS (Package Config Space)
Service 14 “DDR DIMM Digital Thermal Reading”, the value returned is incorrect.
Implication: Platform thermal management may not behave as expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.