Intel® Core™ i7 Processor Family for LGA2011-v3 Socket Specification Update Supporting Desktop Intel® Core™ i7-5960X Extreme Edition Processor Series for the LGA2011-v3 Socket Supporting Desktop Intel® Core™ i7-59xx and i7-58xx Processor Series for the LGA2011-v3 Socket August 2014 Reference Number: 330841-001
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Contents Revision History ........................................................................................................ 4 Preface ...................................................................................................................... 5 Identification Information ......................................................................................... 7 Summary Tables of Changes...................................................................................... 8 Errata ..........
Revision History Version 001 Description Initial release.
Preface This document is an update to the specifications contained in the Affected documents table below. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc.
Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents. Table 1. Processor Signature / Version Reserved Extended family1 Extended model2 Reserved Processor type Family code3 Model number4 Stepping ID5 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0011b 00b 0110b 1111b 0010 Notes: 1.
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes that apply to the processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes used in summary tables Stepping X: Errata exists in the stepping indicated.
Table 3.
Table 4. Specification clarifications No. Specification clarifications None Table 5. Specification Changes No. Specification changes None Table 6. Documentation Changes No.
Errata HSH1 Intel® QPI Layer May Report Spurious Correctable Errors Problem: Intel QPI may report an inband reset with no width change (error 0x22) correctable error upon exit from the L1 power state as logged in its IA32_MC{5, 20, 21}_STATUS MSRs (415H,451H,455H). Implication: An unexpected inband reset with no width change error may be logged. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum.
HSH6 IIO CSR Lnkcon2 Field Selectable_De_Emphasis Cannot Be Set For DMI2 Mode Problem: The CSR lnkcon2 (Bus 0; Device 0; Function 0, Offset 0x1C0) field selectable_de_emphasis (bit 6) cannot be set for a link in DMI2 Mode when the DMI port is operating at 5 GT/s. The documentation has the attribute of RW-O (read, write once), but the processor incorrectly operates as read-only. Implication: When the link is in DMI2 mode, the de-emphasis cannot be changed for an upstream component.
HSH11 CPUID Extended Topology Enumeration Leaf May Indicate an Incorrect Number of Logical Processors Problem: The Extended Topology Enumeration Leaf of CPUID (EAX = 0xB) may return an incorrect value in EBX[15:0] for the core level type (ECX[15:8] = 2). In this instance, the number of logical processors at the core level reported in EBX[15:0] should reflect the configuration as shipped by Intel.
HSH16 System May Hang When Using the TPH Prefetch Hint Problem: When all enabled cores on a socket are simultaneously in core C3, core C6, or package C6 state and a PCIe* TPH (Transaction layer packet Processing Hint) with the prefetch hint set is received, the system may hang. Implication: Due to this erratum, the system may hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the affected steppings, see the Summary Tables of Changes.
HSH21 DDR4 Power Down Timing Violation Problem: When DDR4 is operating at 2133 MHz, the processor’s memory control may violate the JEDEC tPRPDEN timing specification. Implication: Intel has not observed this erratum to impact the operation of any commercially available system Workaround: None identified. Status: For the affected steppings, see the Summary Tables of Changes.
HSH26 Enabling Isochronous Transfers May Result in Unpredictable System Behavior Problem: Enabling isochronous transfers may lead to spurious correctable memory errors, uncorrectable memory errors, patrol scrub errors and unpredictable system behavior. Implication: The system may hang, or report spurious memory errors, or behave unpredictably. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum.
HSH31 Full Duplex NTB Traffic Can Cause a System Hang Problem: If two PCIe* endpoints target traffic to PB23BASE (Bus 0; Device 3; Function 0; Offset 0x18, 0x1c) and PB45BASE (Bus 0; Device 3; Function 0; Offset 0x20, 0x24) registers at the same time, a deadlock can result. Implication: Due to this erratum, the system may hang. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum.
Specification Changes There are no specification changes in this specification update revision.
Specification Clarifications There are no specification clarifications in this specification update revision.
Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® 64 and IA-32 Architectures Software Architecture • Intel® 64 and IA-32 Architectures Software Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software System Programming Guide • Intel® 64 and IA-32 Architectures Software System Programming Guide Developer’s Manual, Volume 1: Basic Develope
