Specification Sheet
Datasheet, Volume 1 of 2 7
2-23 Embedded DisplayPort* (eDP*)/DDI Ports Availability ................................................. 41
2-24 Embedded DisplayPort* (eDP*)/DDI Ports Availability ................................................. 42
2-25 Embedded DisplayPort* (eDP*)/DDI Ports Availability ................................................. 42
2-26 Display Technologies Support .................................................................................. 43
2-27 Display Resolutions and Link Bandwidth for Multi-Stream Transport Calculations............. 43
2-28 Processor Supported Audio Formats Over HDMI* and DisplayPort* ............................... 48
2-29 Maximum Display Resolution................................................................................... 48
2-30 U-Processor Display Resolution Configuration ............................................................ 49
2-31 H/S -Processor Line Display Resolution Configuration ................................................. 49
2-32 HDCP Display supported Implications Table................................................................ 50
2-33 Display Link Data Rate Support ................................................................................ 50
2-34 Display Resolution and Link Rate Support .................................................................. 50
2-35 Display Bit Per Pixel (BPP) Support .......................................................................... 51
2-36 Supported Resolutions for HBR (2.7 Gbps) by Link Width............................................ 51
2-37 Supported Resolutions for HBR2 (5.4 Gbps) by Link Width .......................................... 51
4-1 System States ....................................................................................................... 69
4-2 Processor IA Core / Package State Support ................................................................ 70
4-3 Integrated Memory Controller (IMC) States................................................................ 70
4-4 PCI Express* Link States......................................................................................... 70
4-5 Direct Media Interface (DMI) States.......................................................................... 70
4-6 G, S, and C Interface State Combinations .................................................................. 71
4-7 Deepest Package C-State Available ........................................................................... 78
4-8 Targeted Memory State Conditions ........................................................................... 81
4-9 Package C-States with PCIe* Link States Dependencies............................................... 82
5-1 Configurable TDP Modes.......................................................................................... 91
5-2 TDP Specifications (HU-Processor Line) ..................................................................... 99
5-3 Package Turbo Specifications (HU-Processor Line) ...................................................... 99
5-4 Junction Temperature Specifications ....................................................................... 100
5-5 TDP Specifications (S-Processor Line) ..................................................................... 101
5-6 Low Power and TTV Specifications (S-Processor Line) ................................................ 102
5-7 Package Turbo Specifications (S-Processor Lines) ..................................................... 103
5-9 Thermal Test Vehicle Thermal Profile for PCG 2015D Processor................................... 104
5-8 T
CONTROL
Offset Configuration (S-Processor Line - Client)........................................... 104
5-10 Thermal Test Vehicle Thermal Profile for PCG 2015C Processor ................................... 105
5-11 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor ................................... 106
5-12 Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T
CONTROL
......... 108
5-13 Thermal Margin Slope ........................................................................................... 110
6-1 Signal Tables Terminology ..................................................................................... 111
6-2 LPDDR3 Memory Interface..................................................................................... 111
6-3 DDR4 Memory Interface ........................................................................................ 112
6-4 System Memory Reference and Compensation Signals............................................... 114
6-5 PCI Express* Interface.......................................................................................... 114
6-6 DMI Interface Signals ........................................................................................... 114
6-7 Reset and Miscellaneous Signals............................................................................. 115
6-8 embedded DisplayPort* Signals.............................................................................. 116
6-9 Display Interface Signals ....................................................................................... 116
6-10 Processor Clocking Signals..................................................................................... 117
6-11 Testability Signals ................................................................................................ 117
6-12 Error and Thermal Protection Signals ...................................................................... 118
6-13 Power Sequencing Signals ..................................................................................... 118
6-14 Processor Power Rails Signals ................................................................................ 119
6-15 Processor Ground Rails Signals............................................................................... 120
6-16 GND, RSVD, and NCTF Signals ............................................................................... 121
6-17 Processor Internal Pull-Up / Pull-Down Terminations ................................................. 121
7-1 Processor Power Rails ........................................................................................... 122