Specification Sheet

6 Datasheet, Volume 1 of 2
Figures
1-1 S/H-Processor Line Platforms .................................................................................. 11
1-2 U-Processor Line Platform ....................................................................................... 12
2-1 Intel
®
Flex Memory Technology Operations ............................................................... 24
2-2 Interleave (IL) and Non-Interleave (NIL) Modes Mapping ............................................ 27
2-3 PCI Express* Related Register Structures in the Processor .......................................... 31
2-4 Example for DMI Lane Reversal Connection ............................................................... 33
2-5 Video Analytics Common Use Cases ......................................................................... 38
2-6 Gen 9 LP Block Diagram ......................................................................................... 39
2-7 Processor Display Architecture (With 3 DDI Ports as an Example)................................. 45
2-8 DisplayPort* Overview............................................................................................ 46
2-9 HDMI* Overview ................................................................................................... 47
2-10 Example for PECI Host-Clients Connection................................................................. 52
2-11 Example for PECI EC Connection............................................................................. 53
3-1 Device to Domain Mapping Structures ...................................................................... 57
4-1 Processor Power States .......................................................................................... 68
4-2 Processor Package and IA Core C-States................................................................... 69
4-3 Idle Power Management Breakdown of the Processor IA Cores ..................................... 72
4-4 Package C-State Entry and Exit ............................................................................... 76
5-1 Package Power Control ........................................................................................... 89
5-2 Thermal Test Vehicle Thermal Profile for PCG 2015D Processor ...................................104
5-3 Thermal Test Vehicle Thermal Profile for PCG 2015C Processor ...................................105
5-4 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor ...................................106
5-5 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location .............107
5-6 Digital Thermal Sensor (DTS) 1.1 Definition Points ....................................................108
5-7 Digital Thermal Sensor (DTS) 1.1 Definition Points ....................................................110
7-1 Input Device Hysteresis .........................................................................................138
Tables
1-1 Processor Lines ..................................................................................................... 10
1-2 Terminology.......................................................................................................... 15
1-3 Related Documents ................................................................................................ 18
2-1 Processor DDR Memory Speed Support..................................................................... 19
2-2 Supported DDR4 Non-ECC UDIMM Module Configurations(S-Processor Lines)................. 20
2-3 Supported DDR4 Non-ECC SODIMM Module Configurations(H/U-Processor Lines) ........... 21
2-4 Supported DDR4 ECC SODIMM Module Configurations(S/H-Processor Lines) .................. 21
2-5 Supported DDR4 Memory Down Device Configurations(H/U-Processor Lines) ................. 21
2-6 Supported LPDDR3 x32 DRAMs Configurations(U/H-Processor Line).............................. 21
2-7 Supported LPDDR3 x64 DRAMs Configurations(U-Processor Line) ................................. 22
2-8 DRAM System Memory Timing Support ..................................................................... 22
2-9 DRAM System Memory Timing Support (LPDDR3) ...................................................... 23
2-10 ECC H-Matrix Syndrome Codes ................................................................................ 25
2-11 Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping ....................................... 26
2-12 PCI Express* Bifurcation and Lane Reversal Mapping.................................................. 29
2-13 PCI Express* Maximum Transfer Rates and Theoretical Bandwidth ............................... 30
2-14 Hardware Accelerated Video Decoding ...................................................................... 35
2-15 Hardware Accelerated Video Encode ......................................................................... 36
2-16 Switchable/Hybrid Graphics Support......................................................................... 37
2-17 GT2/3 Graphics Frequency (S/H/U-Processor Line) ..................................................... 39
2-18 DDI Ports Availability ............................................................................................. 40
2-19 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-20 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-21 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-22 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41