Specification Sheet

Processor Graphics Registers
114 Datasheet, Volume 2 of 2
4.12 I/O Base Address (IOBAR)—Offset 20h
This register provides the Base offset of the I/O registers within Device #2. Bits 15:6
are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address
Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of IO space is allowed in PM state D0
when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1-D3 or if IO
Enable is clear or if Device #2 is turned off or if Processor Graphics is disabled through
the fuse or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device #2.
If accesses to this IO bar is allowed then all 8, 16 or 32 bit IO cycles from IA cores that
falls within the 8B are claimed. This IO BAR can be disabled and hidden from system
software via DEV2CTL[0] IOBARDIS at offset 0
Access Method
Default: 1h
27
0h
RW_L
ADMSK256: This bit is either part of the Memory Base Address (R/W) or part of the
Address Mask (RO), depending on the value of MSAC[4:0].
See MSAC (Dev 2, Func 0, offset 62h) for details.
26:4
0h
RO
ADM: Hardwired to 0s to indicate at least 128MB address range.
3
1h
RO
PREFMEM: Hardwired to 1 to enable prefetching.
2:1
2h
RO
MEMTYP: Memory Type (MEMTYP):
00: indicate 32-bit address.
10: Indicate 64-bit address
0
0h
RO
MIOS: Hardwired to 0 to indicate memory space.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:2, F:0] + 20h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RSVD
IOBASE
RSVD
MEMTYPE
MIOS