Specification Sheet
Datasheet, Volume 2 of 2 113
Processor Graphics Registers
4.11 Graphics Memory Range Address (GMADR)—
Offset 18h
GMADR is the PCI aperture used by S/W to access tiled GFX surfaces in a linear fashion.
Access Method
Default: Ch
3
0h
RO
PREFMEM: Hardwired to 0 to prevent prefetching.
2:1
2h
RO
MEMTYP:
00: To indicate 32 bit base address
01: Reserved
10: To indicate 64 bit base address
11: Reserved
0
0h
RO
MIOS: Hardwired to 0 to indicate memory space.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:2, F:0] + 18h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
RSVDRW
MBA
ADMSK4096
ADMSK2048
ADMSK1024
ADMSK512
ADMSK256
ADM
PREFMEM
MEMTYP
MIOS
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RW
RSVDRW: should be set to 0 since addressing above 512GB is not supported.
38:32
0h
RW
MBA: Memory Base Address (MBA): Set by the OS, these bits correspond to address
signals [38:32].
31
0h
RW_L
ADMSK4096: This Bit is either part of the Memory Base Address (R/W) or part of the
Address Mask (RO), depending on the value of MSAC[4:0].
See MSAC (Dev2, Func 0, offset 62h) for details.
30
0h
RW_L
ADMSK2048: This Bit is either part of the Memory Base Address (R/W) or part of the
Address Mask (RO), depending on the value of MSAC[4:0].
See MSAC (Dev2, Func 0, offset 62h) for details.
29
0h
RW_L
ADMSK1024: This Bit is either part of the Memory Base Address (R/W) or part of the
Address Mask (RO), depending on the value of MSAC[4:0].
See MSAC (Dev2, Func 0, offset 62h) for details.
28
0h
RW_L
ADMSK512: This Bit is either part of the Memory Base Address (R/W) or part of the
Address Mask (RO), depending on the value of MSAC[4:0].
See MSAC (Dev2, Func 0, offset 62h) for details.