Specification Sheet

Datasheet, Volume 2 of 2 111
Processor Graphics Registers
4.8 Master Latency Timer (MLT2)—Offset Dh
The Processor Graphics does not support the programmability of the master latency
timer because it does not perform bursts.
Access Method
Default: 0h
4.9 Header Type (HDR2)—Offset Eh
This register contains the Header Type of the Processor Graphics.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RW
CLS: This field is implemented by PCI Express devices as a read-write field for legacy
compatibility purposes but has no effect on any PCI Express device behavior.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + Dh
7 4 0
0 0 0 0 0 0 0 0
MLTCV
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
MLTCV: Hardwired to 0s.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + Eh
7 4 0
0 0 0 0 0 0 0 0
MFUNC
H