Specification Sheet

Processor Graphics Registers
110 Datasheet, Volume 2 of 2
4.6 Class Code (CC)—Offset 9h
This register contains the device programming interface information related to the Sub-
Class Code and Base Class Code definition for the Processor Graphics. This register also
contains the Base Class Code and the function sub-class in relation to the Base Class
Code.
Access Method
Default: 30000h
4.7 Cache Line Size (CLS)—Offset Ch
This register is implemented by PCI Express devices as a read-write field for legacy
compatibility purposes but has no effect on any PCI Express device behavior.
Access Method
Default: 0h
Type: CFG
(Size: 24 bits)
Offset: [B:0, D:2, F:0] + 9h
2
3
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCC
SUBCC
PI
Bit
Range
Default &
Access
Field Name (ID): Description
23:16
3h
RO_V
BCC: This is an 8-bit value that indicates the base class code.
When MGGC0[VAMEN] is 0 this code has the value 03h, indicating a Display Controller.
When MGGC0[VAMEN] is 1 this code has the value 04h, indicating a Multimedia
Device.
15:8
0h
RO_V
SUBCC: When MGGC0[VAMEN] is 0 this value will be determined based on Device 0
GGC register, GMS and IVD fields.
00h: VGA compatible
80h: Non VGA (GMS = “00h” or IVD = “1b”)
When MGGC0[VAMEN] is 1, this value is 80h, indicating other multimedia device.
7:0
0h
RO
PI: When MGGC0[VAMEN] is 0 this value is 00h, indicating a Display Controller.
When MGGC0[VAMEN] is 1 this value is 00h, indicating a NOP.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + Ch
7 4 0
0 0 0 0 0 0 0 0
CLS