Specification Sheet

Datasheet, Volume 2 of 2 109
Processor Graphics Registers
4.5 Revision Identification (RID2)—Offset 8h
This register contains the revision number for Device #2 Functions 0.
These bits are read only and writes to this register have no effect.
Access Method
Default: 0h
6
0h
RO
UDF: Hardwired to 0.
5
0h
RO
C66: N/A - Hardwired to 0.
4
1h
RO
CLIST: This bit is set to 1 to indicate that the register at 34h provides an offset into
the function's PCI Configuration Space containing a pointer to the location of the first
item in the list.
3
0h
RO_V
INTSTS: This bit reflects the state of the interrupt in the device. Only when the
Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1,
will the devices INTx# signal be asserted.
2:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 8h
7 4 0
0 0 0 0 0 0 0 0
RID_MSB
RID
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
0h
RO
RID_MSB: Four MSB of RID
3:0
0h
RO
RID: Four LSB of RID