Specification Sheet

Processor Graphics Registers
108 Datasheet, Volume 2 of 2
4.4 PCI Status (PCISTS2)—Offset 6h
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the Processor Graphics.
Access Method
Default: 10h
2
0h
RW
BME:
0: Disable Processor Graphics bus mastering.
1: Enable the Processor Graphics to function as a PCI compliant master.
1
0h
RW
MAE: This bit controls the Processor Graphics's response to memory space accesses.
0: Disable.
1: Enable.
0
0h
RW
IOAE: This bit controls the Processor Graphics's response to I/O space accesses.
0: Disable.
1: Enable.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + 6h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
DPE
SSE
RMAS
RTAS
STAS
DEVT
DPD
FB2B
UDF
C66
CLIST
INTSTS
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
DPE: Since the Processor Graphics does not detect parity, this bit is always hardwired
to 0.
14
0h
RO
SSE: The Processor Graphics never asserts SERR#, therefore this bit is hardwired to 0.
13
0h
RO
RMAS: The Processor Graphics never gets a Master Abort, therefore this bit is
hardwired to 0.
12
0h
RO
RTAS: The Processor Graphics never gets a Target Abort, therefore this bit is
hardwired to 0.
11
0h
RO
STAS: Hardwired to 0. The Processor Graphics does not use target abort semantics.
10:9
0h
RO
DEVT: N/A. These bits are hardwired to "00".
8
0h
RO
DPD: Since Parity Error Response is hardwired to disabled (and the Processor Graphics
does not do any parity detection), this bit is hardwired to 0.
7
0h
RO
FB2B: Hardwired to 0.