Specification Sheet

Datasheet, Volume 2 of 2 107
Processor Graphics Registers
4.3 PCI Command (PCICMD)—Offset 4h
This 16-bit register provides basic control over the Processor Graphics's ability to
respond to PCI cycles. The PCICMD Register in the Processor Graphics disables the
Processor Graphics PCI compliant master accesses to main memory.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + 4h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
INTDIS
FB2B
SEN
WCC
PER
VPS
MWIE
SCE
BME
MAE
IOAE
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
0h
RO
Reserved (RSVD): Reserved.
10
0h
RW
INTDIS: This bit disables the device from asserting INTx#.
0: Enable the assertion of this device's INTx# signal.
1: Disable the assertion of this device's INTx# signal. DO_INTx messages will not be
sent to DMI.
9
0h
RO
FB2B: Not Implemented. Hardwired to 0.
8
0h
RO
SEN: Not Implemented. Hardwired to 0.
7
0h
RO
WCC: Not Implemented. Hardwired to 0.
6
0h
RO
PER: Not Implemented. Hardwired to 0. Since the Processor Graphics belongs to the
category of devices that does not corrupt programs or data in system memory or hard
drives, the Processor Graphics ignores any parity error that it detects and continues
with normal operation.
5
0h
RO
VPS: This bit is hardwired to 0 to disable snooping.
4
0h
RO
MWIE: Hardwired to 0. The Processor Graphics does not support memory write and
invalidate commands.
3
0h
RO
SCE: This bit is hardwired to 0. The Processor Graphics ignores Special cycles.