Specification Sheet

Datasheet, Volume 2 of 2 9
10.31 IOTLB Invalidate Register (IOTLB)—Offset 508h .................................................. 312
11 IMGU Registers ..................................................................................................... 315
11.1 Vendor Identification (VID)—Offset 0h ............................................................... 316
11.2 Device Identification (DID)—Offset 2h................................................................ 316
11.3 PCI Command (PCICMD)—Offset 4h................................................................... 317
11.4 PCI Status (PCISTS)—Offset 6h......................................................................... 318
11.5 Revision Identification and Class Code (RID)—Offset 8h........................................ 319
11.6 Cache Line Size (CLS)—Offset Ch ...................................................................... 319
11.7 Master Latency Timer (MLT)—Offset Dh.............................................................. 320
11.8 Header Type (HDR)—Offset Eh .......................................................................... 320
11.9 Built In Self Test (BIST)—Offset Fh .................................................................... 321
11.10 IMGU Memory Mapped Register Range Base (IMGBAR)—Offset 10h........................ 321
11.11 Subsystem Vendor Identification (SVID)—Offset 2Ch ........................................... 322
11.12 Subsystem Identification (SID)—Offset 2Eh ........................................................ 323
11.13 Capabilities Pointer (CAPPOINT)—Offset 34h ....................................................... 323
11.14 Interrupt Line (INTRLINE)—Offset 3Ch ............................................................... 324
11.15 Interrupt Pin (INTRPIN)—Offset 3Dh .................................................................. 324
11.16 Message Signaled Interrupts Capability ID (MSI)—Offset 90h ................................ 325
11.17 Message Control (MC)—Offset 92h..................................................................... 325
11.18 Message Address (MA)—Offset 94h.................................................................... 326
11.19 Message Address (MA)—Offset 98h.................................................................... 327
11.20 Message Data (MD)—Offset 9Ch........................................................................ 327
11.21 Advanced Features Capabilities - ID and Next Pointer (AFCIDNP)—Offset A0h.......... 328
11.22 Advanced Features Length and Capabilities (AFLC)—Offset A2h ............................. 328
11.23 Advanced Features Control (AFCTL)—Offset A4h.................................................. 329
11.24 Advanced Features Status (AFSTS)—Offset A5h................................................... 330
11.25 Power Management Control and Status (PMCS)—Offset D4h.................................. 330
12 PCI Express* Controller (x16) Registers................................................................ 332
12.1 Vendor Identification (VID)—Offset 0h ............................................................... 334
12.2 Device Identification (DID)—Offset 2h................................................................ 334
12.3 PCI Command (PCICMD)—Offset 4h................................................................... 335
12.4 PCI Status (PCISTS)—Offset 6h......................................................................... 336
12.5 Revision Identification (RID)—Offset 8h.............................................................. 338
12.6 Class Code (CC)—Offset 9h............................................................................... 338
12.7 Cache Line Size (CL)—Offset Ch ........................................................................ 339
12.8 Header Type (HDR)—Offset Eh .......................................................................... 339
12.9 Primary Bus Number (PBUSN)—Offset 18h.......................................................... 340
12.10 Secondary Bus Number (SBUSN)—Offset 19h...................................................... 340
12.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah ................................................. 341
12.12 I/O Base Address (IOBASE)—Offset 1Ch............................................................. 342
12.13 I/O Limit Address (IOLIMIT)—Offset 1Dh ............................................................ 342
12.14 Secondary Status (SSTS)—Offset 1Eh ................................................................ 343
12.15 Memory Base Address (MBASE)—Offset 20h ....................................................... 344
12.16 Memory Limit Address (MLIMIT)—Offset 22h....................................................... 345
12.17 Prefetchable Memory Base Address (PMBASE)—Offset 24h.................................... 346
12.18 Prefetchable Memory Limit Address (PMLIMIT)—Offset 26h ................................... 346
12.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h ........................ 347
12.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch........................ 348
12.21 Capabilities Pointer (CAPPTR)—Offset 34h........................................................... 349
12.22 Interrupt Line (INTRLINE)—Offset 3Ch ............................................................... 349
12.23 Interrupt Pin (INTRPIN)—Offset 3Dh .................................................................. 350
12.24 Bridge Control (BCTRL)—Offset 3Eh ................................................................... 351
12.25 Power Management Capabilities (PM)—Offset 80h................................................ 352
12.26 Power Management Control/Status (PM)—Offset 84h ........................................... 353