Specification Sheet

Datasheet, Volume 2 of 2 105

Processor Graphics Registers

4 Processor Graphics Registers

Table 4-1. Summary of Bus: 0, Device: 2, Function: 0 (CFG)

Offset

Size

(Bytes)

0–1h 2 Vendor Identification (VID2)—Offset 0h 8086h

2–3h 2 Device Identification (DID2)—Offset 2h 59XXh

4–5h 2 PCI Command (PCICMD)—Offset 4h 0h

6–7h 2 PCI Status (PCISTS2)—Offset 6h 10h

8–8h 1 Revision Identification (RID2)—Offset 8h 0h

9–Bh 3 Class Code (CC)—Offset 9h 30000h

C–Ch 1 Cache Line Size (CLS)—Offset Ch 0h

D–Dh 1 Master Latency Timer (MLT2)—Offset Dh 0h

E–Eh 1 Header Type (HDR2)—Offset Eh 0h

10–17h 8

Graphics Translation Table, Memory Mapped Range Address

(GTTMMADR)—Offset 10h

18–1Fh 8 Graphics Memory Range Address (GMADR)—Offset 18h Ch

20–23h 4 I/O Base Address (IOBAR)—Offset 20h 1h

2C–2Dh 2 Subsystem Vendor Identification (SVID2)—Offset 2Ch 0h

2E–2Fh 2 Subsystem Identification (SID2)—Offset 2Eh 0h

30–33h 4 Video BIOS ROM Base Address (ROMADR)—Offset 30h 0h

34–34h 1 Capabilities Pointer (CAPPOINT)—Offset 34h 40h

3C–3Ch 1 Interrupt Line (INTRLINE)—Offset 3Ch 0h

3D–3Dh 1 Interrupt Pin (INTRPIN)—Offset 3Dh 1h

3E–3Eh 1 Minimum Grant (MINGNT)—Offset 3Eh 0h

3F–3Fh 1 Maximum Latency (MAXLAT)—Offset 3Fh 0h

44–47h 4 Capabilities A (CAPID0)—Offset 44h 0h

48–4Bh 4 Capabilities B (CAPID0)—Offset 48h 0h

54–57h 4 Device Enable (DEVEN0)—Offset 54h 84BFh

5C–5Fh 4 Base Data of Stolen Memory (BDSM)—Offset 5Ch 0h

62–62h 1 Multi Size Aperture Control (MSAC)—Offset 62h 1h

70–71h 2 PCI Express Capability Header (PCIECAPHDR)—Offset 70h AC10h

AC–ADh 2 Message Signaled Interrupts Capability ID (MSI)—Offset ACh D005h

AE–AFh 2 Message Control (MC)—Offset AEh 0h

B0–B3h 4 Message Address (MA)—Offset B0h 0h

B4–B5h 2 Message Data (MD)—Offset B4h 0h

D0–D1h 2 Power Management Capabilities ID (PMCAPID)—Offset D0h 1h

D2–D3h 2 Power Management Capabilities (PMCAP)—Offset D2h

22h

D4–D5h 2 Power Management Control/Status (PMCS)—Offset D4h 0h