Specification Sheet
Host Bridge/DRAM Registers
100 Datasheet, Volume 2 of 2
3.41 Capabilities C (CAPID0)—Offset ECh
Control of bits in this register are only required for customer visible SKU differentiation.
Access Method
Default: 0h
§ §
6:4
0h
RO
DMFC_DDR3: This field controls which values may be written to the Memory
Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset
C00h). Any attempt to write an unsupported value will be ignored.
000: MC capable of DDR3 2667 (2667 is the upper limit)
001: MC capable of up to DDR3 2667
010: MC capable of up to DDR3 2400
011: MC capable of up to DDR3 2133
100: MC capable of up to DDR3 1867
101: MC capable of up to DDR3 1600
110: MC capable of up to DDR3 1333
111: MC capable of up to DDR3 1067
3
0h
RO
Reserved (RSVD): Reserved.
2
0h
RO
LPDDR3_EN: Allow LPDDR3 operation
1:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + ECh
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
DMFC_DDR4
DMFC_LPDDR3
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RO
Reserved (RSVD): Reserved.
19:17
0h
RO
DMFC_DDR4: hardware will update this field with the value of FUSE_DMFC_DDR4.
16:14
0h
RO
DMFC_LPDDR3: hardware will update this field with the value of
FUSE_DMFC_LPDDR3.
13:0
0h
RO
Reserved (RSVD): Reserved.