Specification Sheet
Datasheet, Volume 2 of 2 99
Host Bridge/DRAM Registers
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO_KFW
IMGU_DIS:
0: Device 5 associated memory spaces are accessible.
1: Device 5 associated memory and IO spaces are disabled by hardwiring the D1F2EN
field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
30:29
0h
RO
Reserved (RSVD): Reserved.
28
0h
RO
SMT: This setting indicates whether or not the Processor is SMT capable.
27:25
0h
RO
CACHESZ: This setting indicates the supporting cache sizes.
24
0h
RO
Reserved (RSVD): Reserved.
23:21
0h
RO
PLL_REF100_CFG: DDR3 Maximum Frequency Capability with 100 Memory.
hardware will update this field with the value of FUSE_PLL_REF100_CFG and then
apply SSKU overrides.
Maximum allowed memory frequency with 100 MHz ref clk. Also serves as defeature.
Unlike 133 MHz ref fuses, these are normal 3 bit field
0: 100 MHz ref disabled
1: up to DDR-1400 (7 x 200)
2: up to DDR-1600 (8 x 200)
3: up to DDR-1800 (8 x 200)
4: up to DDR-2000 (10 x 200)
5: up to DDR-2200 (11 x 200)
6: up to DDR-2400 (12 x 200)
7: no limit (but still limited by _DDR_FREQ200 to 2600)
20
0h
RO
PEGG3_DIS: the processor: PCIe Gen 3 Disable fuse. This fuse will be strap
selectable/modifiable to enable SSKU capabilities. This is a defeature fuse -- an un-
programmed device should have PCIe Gen 3 capabilities enabled.
0: Capable of running any of the Gen 3-compliant PEG controllers in Gen 3 mode
(Devices 0/1/0, 0/1/1, 0/1/2)
1: Not capable of running any of the PEG controllers in Gen 3 mode
19
0h
RO
Reserved (RSVD): Reserved.
18
0h
RO
ADDGFXEN:
0: Additive Graphics Disabled
1: Additive Graphics Enabled
17
0h
RO
ADDGFXCAP:
0: Capable of Additive Graphics
1: Not capable of Additive Graphics
16
0h
RO
Reserved (RSVD): Reserved.
15
0h
RO
DMIG3DIS: DMI Gen 3 Disable fuse.
14:9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RO_KFW
GMM_DIS:
0: Device 8 associated memory spaces are accessible.
1: Device 8 associated memory and IO spaces are disabled by hardwiring the D8EN
field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
7
0h
RO
Reserved (RSVD): Reserved.