Specification Sheet

Host Bridge/DRAM Registers
96 Datasheet, Volume 2 of 2
According to the above equation, TOLUD is originally calculated to: 4GB =
1_0000_0000h
The system memory requirements are: 4GB (max addressable space) - 1GB (pci
space) - 35MB (lost memory) = 3GB - 35MB (minimum granularity) = 0_ECB0_0000h
Since 0_ECB0_0000h (PCI and other system requirements) is less than
1_0000_0000h, TOLUD should be programmed to ECBh.
These bits are Intel TXT lockable.
Access Method
Default: 100000h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + BCh
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TOLUD
RSVD
LOCK
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
1h
RW_L
TOLUD: This register contains bits 31 to 20 of an address one byte above the
maximum DRAM memory below 4G that is usable by the operating system. Address
bits 31 down to 20 programmed to 01h implies a minimum memory size of 1 MB.
Configuration software should set this value to the smaller of the following 2 choices:
maximum amount memory in the system minus ME stolen memory plus one byte or
the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be
0_0000h for the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less than the value
programmed in this register.
The Top of Low Usable DRAM is the lowest address above both Graphics Stolen
memory and Tseg. BIOS determines the base of Graphics Stolen Memory by
subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by
Tseg size to determine base of Tseg. All the Bits in this register are locked in Intel TXT
mode.
This register should be 1 MB aligned when reclaim is enabled.
19:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW_KL
LOCK: This bit will lock all writeable settings in this register, including itself.