Specification Sheet

Datasheet, Volume 2 of 2 95
Host Bridge/DRAM Registers
3.36 TSEG Memory Base (TSEGMB)—Offset B8h
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory which should be at or below Graphics Base of GTT Stolen
Memory (PCI Device 0 Offset B4 bits 31:20).
Access Method
Default: 0h
3.37 Top of Low Usable DRAM (TOLUD)—Offset BCh
This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory
and Graphics Stolen Memory are within the DRAM space defined. From the top, the
Host optionally claims 1 to 64MBs of DRAM for Processor Graphics if enabled, 1or 2MB
of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for
TSEG if enabled.
Programming Example:
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Processor Graphics is enabled, and Graphics Mode Select is set to 32 MB
GTT Graphics Stolen Memory Size set to 2 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by
the system. This 20 MB range at the very top of addressable memory space is lost
to APIC and Intel TXT.
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + B8h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSEGMB
RSVD
LOCK
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RW_L
TSEGMB: This register contains the base address of TSEG DRAM memory. BIOS
determines the base of TSEG memory which should be at or below Graphics Base of
GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20). BIOS should program the
value of TSEGMB to be the same as BGSM when TSEG is disabled.
19:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW_KL
LOCK: This bit will lock all writeable settings in this register, including itself.