Specification Sheet

8 Datasheet, Volume 2 of 2
8.13 Advanced Fault Log Register (AFLOG)—Offset 58h................................................254
8.14 Protected Memory Enable Register (PMEN)—Offset 64h.........................................255
8.15 Protected Low-Memory Base Register (PLMBASE)—Offset 68h................................256
8.16 Protected Low-Memory Limit Register (PLMLIMIT)—Offset 6Ch...............................257
8.17 Protected High-Memory Base Register (PHMBASE)—Offset 70h ..............................258
8.18 Protected High-Memory Limit Register (PHMLIMIT)—Offset 78h..............................259
8.19 Invalidation Queue Head Register (IQH)—Offset 80h ............................................260
8.20 Invalidation Queue Tail Register (IQT)—Offset 88h ...............................................261
8.21 Invalidation Queue Address Register (IQA)—Offset 90h.........................................262
8.22 Invalidation Completion Status Register (ICS)—Offset 9Ch ....................................263
8.23 Invalidation Event Control Register (IECTL)—Offset A0h........................................264
8.24 Invalidation Event Data Register (IEDATA)—Offset A4h.........................................265
8.25 Invalidation Event Address Register (IEADDR)—Offset A8h....................................265
8.26 Invalidation Event Upper Address Register (IEUADDR)—Offset ACh ........................266
8.27 Interrupt Remapping Table Address Register (IRTA)—Offset B8h............................267
8.28 Fault Recording Low Register (FRCDL)—Offset 400h .............................................268
8.29 Fault Recording High Register (FRCDH)—Offset 408h............................................268
8.30 Invalidate Address Register (IVA)—Offset 500h....................................................270
8.31 IOTLB Invalidate Register (IOTLB)—Offset 508h...................................................271
8.32 DMA Remap Engine Policy Control (ARCHDIS)—Offset FF0h ...................................273
8.33 DMA Remap Engine Policy Control (UARCHDIS)—Offset FF4h .................................275
9 PXPEPBAR Registers ..............................................................................................277
9.1 EP VC 0 Resource Control (EPVC0RCTL)—Offset 14h.............................................277
10 VC0PREMAP Registers............................................................................................279
10.1 Version Register (VER)—Offset 0h......................................................................280
10.2 Capability Register (CAP)—Offset 8h...................................................................280
10.3 Extended Capability Register (ECAP)—Offset 10h .................................................283
10.4 Global Command Register (GCMD)—Offset 18h....................................................285
10.5 Global Status Register (GSTS)—Offset 1Ch..........................................................288
10.6 Root-Entry Table Address Register (RTADDR)—Offset 20h .....................................289
10.7 Context Command Register (CCMD)—Offset 28h..................................................290
10.8 Fault Status Register (FSTS)—Offset 34h ............................................................292
10.9 Fault Event Control Register (FECTL)—Offset 38h .................................................293
10.10 Fault Event Data Register (FEDATA)—Offset 3Ch..................................................295
10.11 Fault Event Address Register (FEADDR)—Offset 40h .............................................295
10.12 Fault Event Upper Address Register (FEUADDR)—Offset 44h..................................296
10.13 Advanced Fault Log Register (AFLOG)—Offset 58h................................................296
10.14 Protected Memory Enable Register (PMEN)—Offset 64h.........................................297
10.15 Protected Low-Memory Base Register (PLMBASE)—Offset 68h................................298
10.16 Protected Low-Memory Limit Register (PLMLIMIT)—Offset 6Ch...............................299
10.17 Protected High-Memory Base Register (PHMBASE)—Offset 70h ..............................300
10.18 Protected High-Memory Limit Register (PHMLIMIT)—Offset 78h..............................301
10.19 Invalidation Queue Head Register (IQH)—Offset 80h ............................................302
10.20 Invalidation Queue Tail Register (IQT)—Offset 88h ...............................................303
10.21 Invalidation Queue Address Register (IQA)—Offset 90h.........................................304
10.22 Invalidation Completion Status Register (ICS)—Offset 9Ch ....................................304
10.23 Invalidation Event Control Register (IECTL)—Offset A0h........................................305
10.24 Invalidation Event Data Register (IEDATA)—Offset A4h.........................................306
10.25 Invalidation Event Address Register (IEADDR)—Offset A8h....................................307
10.26 Invalidation Event Upper Address Register (IEUADDR)—Offset ACh ........................308
10.27 Interrupt Remapping Table Address Register (IRTA)—Offset B8h............................308
10.28 Fault Recording Low Register (FRCDL)—Offset 400h .............................................309
10.29 Fault Recording High Register (FRCDH)—Offset 408h............................................310
10.30 Invalidate Address Register (IVA)—Offset 500h....................................................311