Specification Sheet

Datasheet, Volume 2 of 2 89
Host Bridge/DRAM Registers
3.29 System Management RAM Control (SMRAMC)—
Offset 88h
The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated.
The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the
Open bit should be reset before the Lock bit is set.
Access Method
Default: 2h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:0, F:0] + 88h
7 4 0
0 0 0 0 0 0 1 0
RSVD
D_OPEN
D_CLS D_LCK
G_SMRAME
C_BASE_SEG
Bit
Range
Default &
Access
Field Name (ID): Description
7
0h
RO
Reserved (RSVD): Reserved.
6
0h
RW_LV
D_OPEN: When D_OPEN = 1 and D_LCK = 0, the SMM DRAM space is made visible
even when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN = 1 and D_CLS = 1 are not set at the
same time.
5
0h
RW_L
D_CLS: When D_CLS = 1, SMM DRAM space is not accessible to data references, even
if SMM decode is active. Code references may still access SMM DRAM space. This will
allow SMM software to reference through SMM space to update the display even when
SMM is mapped over the VGA range. Software should ensure that D_OPEN = 1 and
D_CLS = 1 are not set at the same time.
4
0h
RW_KL
D_LCK: When D_LCK=1, then D_OPEN is reset to 0 and all writeable fields in this
register are locked (become RO). D_LCK can be set to 1 via a normal configuration
space write but can only be cleared by a Full Reset.
The combination of D_LCK and D_OPEN provide convenience with security. The BIOS
can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock
down" SMM space in the future so that no application software (or even BIOS itself)
can violate the integrity of SMM space, even if the program has knowledge of the
D_OPEN function.
3
0h
RW_L
G_SMRAME: If set to '1', then Compatible SMRAM functions are enabled, providing
128KB of DRAM accessible at the A_0000h address while in SMM. Once D_LCK is set,
this bit becomes RO.
2:0
2h
RO
C_BASE_SEG: This field indicates the location of SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are right to access SMM space,
otherwise the access is forwarded to DMI. Only SMM space between A_0000h and
B_FFFFh is supported, so this field is hardwired to 010b.