Specification Sheet

Datasheet, Volume 2 of 2 87
Host Bridge/DRAM Registers
3
0h
RW
MDAP60: This bit works with the VGA Enable bits in the BCTRL register of Device 1
Function 2 to control the routing of Processor initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set if device 1
function 2 VGA Enable bit is not set.
If device 1 function 2 VGA enable bit is not set, then accesses to IO address range
x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range
x3BCh-x3BFh are forwarded to PCI Express through device 1 function 2 if the address
is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the
backbone.
MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will
remain on the backbone even if the reference also includes I/O locations not listed
above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP Description
0 0 All References to MDA and VGA space are not claimed by Device 1
Function 2.
0 1 Illegal combination
1 0 All VGA and MDA references are routed to PCI Express Graphics
Attach device 1 function 2.
1 1 All VGA references are routed to PCI Express Graphics Attach
device 1 function 2. MDA references are not claimed by device 1
function 2. VGA and MDA memory cycles can only be routed
across PEG12 when MAE (PCICMD12[1]) is set. VGA and MDA I/O
cycles can only be routed across PEG12 if IOAE (PCICMD12[0]) is
set.
2
0h
RW
MDAP12: This bit works with the VGA Enable bits in the BCTRL register of Device 1
Function 2 to control the routing of Processor initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set if device 1
function 2 VGA Enable bit is not set.
If device 1 function 2 VGA enable bit is not set, then accesses to IO address range
x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range
x3BCh-x3BFh are forwarded to PCI Express through device 1 function 2 if the address
is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the
backbone.
MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will
remain on the backbone even if the reference also includes I/O locations not listed
above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP Description
0 0 All References to MDA and VGA space are not claimed by Device
1 Function 2.
0 1 Illegal combination
1 0 All VGA and MDA references are routed to PCI Express Graphics
Attach device 1 function 2.
1 1 All VGA references are routed to PCI Express Graphics Attach
device 1 function 2. MDA references are not claimed by device 1
function 2.
VGA and MDA memory cycles can only be routed across PEG12
when MAE (PCICMD12[1]) is set. VGA and MDA I/O cycles can
only be routed across PEG12 if IOAE (PCICMD12[0]) is set.
Bit
Range
Default &
Access
Field Name (ID): Description