Specification Sheet

Datasheet, Volume 2 of 2 83
Host Bridge/DRAM Registers
Two bits are used to specify memory attributes for each memory segment. These bits
apply to host accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE=1, the host read accesses to the corresponding memory
segment are claimed by the Uncore and directed to main memory. Conversely, when
RE=0, the host read accesses are directed to DMI.
WE - Write Enable. When WE=1, the host write accesses to the corresponding memory
segment are claimed by the Uncore and directed to main memory. Conversely, when
WE=0, the host read accesses are directed to DMI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the
segment is Read Only.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:0, F:0] + 84h
7 4 0
0 0 0 0 0 0 0 0
RSVD
HIENABLE
RSVD
LOENABLE
Bit
Range
Default &
Access
Field Name (ID): Description
7:6
0h
RO
Reserved (RSVD): Reserved.
5:4
0h
RW_L
HIENABLE: This field controls the steering of read and write cycles that address the
BIOS area from 0DC000h to 0DFFFFh.
00: DRAM Disabled. All accesses are directed to DMI.
01: Read Only. All reads are sent to DRAM, all writes are forwarded to DMI.
10: Write Only. All writes are sent to DRAM, all reads are serviced by DMI.
11: Normal DRAM Operation. All reads and writes are serviced by DRAM.
3:2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RW_L
LOENABLE: This field controls the steering of read and write cycles that address the
BIOS area from 0D8000h to 0DBFFFh.
00: DRAM Disabled. All reads are sent to DRAM. All writes are forwarded to DMI.
01: Read Only. All reads are sent to DRAM. All writes are forwarded to DMI.
10: Write Only. All writes are sent to DRAM. All reads are serviced by DMI.
11: Normal DRAM Operation. All reads and writes are serviced by DRAM.