Specification Sheet
Datasheet, Volume 2 of 2 77
Host Bridge/DRAM Registers
Access Method
Default: 7FFFF00000h
3.20 Manageability Engine Limit Address Register
(MESEG)—Offset 78h
This register determines the Mask Address register of the memory range that is pre-
allocated to the Manageability Engine. Together with the MESEG_BASE register it
controls the amount of memory allocated to the ME.
This register is locked by Intel TXT.
Note: BIOS should program MESEG_BASE and MESEG_MASK so that ME Stolen Memory is
carved out from TOM.
Access Method
Default: 0h
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 70h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
MEBASE
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:20
7FFFFh
RW_L
MEBASE: Corresponds to A[38:20] of the base address memory range that is
allocated to the ME.
19:0
0h
RO
Reserved (RSVD): Reserved.
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 78h