Specification Sheet
Host Bridge/DRAM Registers
76 Datasheet, Volume 2 of 2
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and should be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]
All the bits in this register are locked in Intel TXT mode.
Access Method
Default: 0h
3.19 Manageability Engine Base Address Register
(MESEG)—Offset 70h
This register determines the Base Address register of the memory range that is pre-
allocated to the Manageability Engine. Together with the MESEG_MASK register it
controls the amount of memory allocated to the ME.
This register should be initialized by the configuration software. For the purpose of
address decode address bits A[19:0] are assumed to be 0. Thus, the bottom of the
defined memory address range will be aligned to a 1MB boundary.
This register is locked by Intel TXT.
Note: BIOS should program MESEG_BASE and MESEG_MASK so that ME Stolen Memory is
carved out from TOM.
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 68h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
DMIBAR
RSVD
DMIBAREN
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW
DMIBAR: This field corresponds to bits 38 to 12 of the base address DMI
configuration space. BIOS will program this register resulting in a base address for a
4KB block of contiguous memory address space. This register ensures that a naturally
aligned 4KB space is allocated within the first 512GB of addressable memory space.
System Software uses this base address to program the DMI register set. All the Bits
in this register are locked in Intel TXT mode.
11:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW
DMIBAREN:
0: DMIBAR is disabled and does not claim any memory
1: DMIBAR memory mapped accesses are claimed and decoded appropriately
This register is locked by Intel TXT.