Specification Sheet

Datasheet, Volume 2 of 2 75
Host Bridge/DRAM Registers
3.18 Root Complex Register Range Base Address
(DMIBAR)—Offset 68h
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the Host Bridge. There is no physical memory within this 4KB window
that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:28
0h
RW
PCIEXBAR: This field corresponds to bits 38 to 28 of the base address for PCI Express
enhanced configuration space. BIOS will program this register resulting in a base
address for a contiguous memory address space. The size of the range is defined by
bits [2:1] of this register.
This Base address shall be assigned on a boundary consistent with the number of
buses (defined by the Length field in this register) above TOLUD and still within the
39-bit addressable memory space. The address bits decoded depend on the length of
the region defined by this register.
This register is locked by Intel TXT.
The address used to access the PCI Express configuration space for a specific device
can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device Number * 32KB + Function
Number * 4KB
This address is the beginning of the 4KB space that contains both the PCI compatible
configuration space and the PCI Express extended configuration space.
27
0h
RW_V
ADMSK128: This bit is either part of the PCI Express Base Address (R/W) or part of
the Address Mask (RO, read 0b), depending on the value of bits [2:1] in this register.
26
0h
RW_V
ADMSK64: This bit is either part of the PCI Express Base Address (R/W) or part of the
Address Mask (RO, read 0b), depending on the value of bits [2:1] in this register.
25:3
0h
RO
Reserved (RSVD): Reserved.
2:1
0h
RW
LENGTH: This field describes the length of this region.
00: 256MB (buses 0-255). Bits 38:28 are decoded in the PCI Express Base Address
Field.
01: 128MB (buses 0-127). Bits 38:27 are decoded in the PCI Express Base Address
Field.
10: 64MB (buses 0-63). Bits 38:26 are decoded in the PCI Express Base Address Field.
11: Reserved.
This register is locked by Intel TXT.
0
0h
RW
PCIEXBAREN:
0: The PCIEXBAR register is disabled. Memory read and write transactions proceed s if
there were no PCIEXBAR register. PCIEXBAR bits 38:26 are R/W with no functionality
behind them.
1: The PCIEXBAR register is enabled. Memory read and write transactions whose
address bits 38:26 match PCIEXBAR will be translated to configuration reads and
writes within the Uncore. These Translated cycles are routed as shown in the above
table.