Specification Sheet
Datasheet, Volume 2 of 2 73
Host Bridge/DRAM Registers
3.16 DMA Protected Range (DPR)—Offset 5Ch
DMA protected range register.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5Ch
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TopOfDPR
RSVD
DPRSIZE
RSVD
EPM
PRS
LOCK
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
ROV
TopOfDPR: Top address + 1 of DPR. This is the base of TSEG. Bits 19:0 of the BASE
reported here are 0x0_0000.
19:12
0h
RO
Reserved (RSVD): Reserved.
11:4
0h
RW_L
DPRSIZE: This is the size of memory, in MB, that will be protected from DMA
accesses. A value of 0x00 in this field means no additional memory is protected. The
maximum amount of memory that will be protected is 255 MB.
The amount of memory reported in this field will be protected from all DMA accesses,
including translated Processor accesses and graphics. The top of the protected range is
the BASE of TSEG -1.
Note: If TSEG is not enabled, then the top of this range becomes the base of stolen
graphics, or ME stolen space or TOLUD, whichever would have been the location of
TSEG, assuming it had been enabled.
The DPR range works independently of any other range, including the NoDMA.TABLE
protection or the PMRC checks in VTd, and is done post any VTd translation or Intel
TXT NoDMA lookup. Therefore incoming cycles are checked against this range after the
VTd translation and faulted if they hit this protected range, even if they passed the
VTd translation or were clean in the NoDMA lookup.
All the memory checks are OR'ed with respect to NOT being allowed to go to memory.
So if either PMRC, DPR, NoDMA table lookup, NoDMA.TABLE.PROTECT OR a VTd
translation disallows the cycle, then the cycle is not allowed to go to memory. Or in
other words, all the above checks should pass before a cycle is allowed to DRAM.
3
0h
RO
Reserved (RSVD): Reserved.
2
0h
RW_L
EPM: This field controls DMA accesses to the DMA Protected Range (DPR) region.
0: DPR is disabled
1: DPR is enabled. All DMA requests accessing DPR region are blocked.
HW reports the status of DPR enable/disable through the PRS field in this register.
1
0h
ROV
PRS: This field indicates the status of DPR.
0: DPR protection disabled
1: DPR protection enabled
0
0h
RW_KL
LOCK: All bits which may be updated by SW in this register are locked down when this
bit is set.