Specification Sheet

6 Datasheet, Volume 2 of 2
6.27 DMI Uncorrectable Error Mask (DMIUEMSK)—Offset 1C8h .....................................148
6.28 DMI Uncorrectable Error Severity (DMIUESEV)—Offset 1CCh .................................149
6.29 DMI Correctable Error Status (DMICESTS)—Offset 1D0h .......................................150
6.30 DMI Correctable Error Mask (DMICEMSK)—Offset 1D4h ........................................151
7 MCHBAR Registers .................................................................................................152
7.1 MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR—Offset 4000h...................................154
7.2 MCHBAR_CH0_CR_SC_GS_CFG_0_0_0_MCHBAR—Offset 401Ch ............................155
7.3 MCHBAR_CH0_CR_TC_ODT_0_0_0_MCHBAR—Offset 4070h..................................157
7.4 Refresh parameters (TC)—Offset 4238h..............................................................158
7.5 Refresh timing parameters (TC)—Offset 423Ch ....................................................159
7.6 Power Management DIMM Idle Energy (PM)—Offset 4260h....................................160
7.7 Power Management DIMM Power Down Energy (PM)—Offset 4264h ........................161
7.8 Power Management DIMM Activate Energy (PM)—Offset 4268h ..............................162
7.9 Power Management DIMM RdCas Energy (PM)—Offset 426Ch ................................163
7.10 Power Management DIMM WrCas Energy (PM)—Offset 4270h ................................164
7.11 MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR—Offset 4400h...................................165
7.12 MCHBAR_CH0_CR_SC_GS_CFG_0_0_0_MCHBAR—Offset 441Ch ............................166
7.13 MCHBAR_CH0_CR_TC_ODT_0_0_0_MCHBAR—Offset 4470h..................................168
7.14 Refresh parameters (TC)—Offset 4638h..............................................................169
7.15 Refresh timing parameters (TC)—Offset 463Ch ....................................................170
7.16 Power Management DIMM Idle Energy (PM)—Offset 4660h....................................171
7.17 Power Management DIMM Power Down Energy (PM)—Offset 4664h ........................172
7.18 Power Management DIMM Activate Energy (PM)—Offset 4668h ..............................173
7.19 Power Management DIMM RdCas Energy (PM)—Offset 466Ch ................................174
7.20 Power Management DIMM WrCas Energy (PM)—Offset 4670h ................................175
7.21 MCSCHEDS_CR_SC_GS_CFG_0_0_0_MCHBAR—Offset 4C1Ch................................176
7.22 PM—Offset 4C40h ............................................................................................177
7.23 MCSCHEDS_CR_TC_ODT_0_0_0_MCHBAR—Offset 4C70h .....................................178
7.24 Refresh parameters (TC)—Offset 4E38h..............................................................179
7.25 Refresh timing parameters (TC)—Offset 4E3Ch ....................................................180
7.26 Power Management DIMM Idle Energy (PM)—Offset 4E60h....................................180
7.27 Power Management DIMM Power Down Energy (PM)—Offset 4E64h ........................181
7.28 Power Management DIMM Activate Energy (PM)—Offset 4E68h ..............................182
7.29 Power Management DIMM RdCas Energy (PM)—Offset 4E6Ch ................................183
7.30 Power Management DIMM WrCas Energy (PM)—Offset 4E70h ................................184
7.31 Address decoder inter channel configuration register (MAD)—Offset 5000h ..............185
7.32 Address decoder intra channel configuration register (MAD)—Offset 5004h ..............186
7.33 Address decoder intra channel configuration register (MAD)—Offset 5008h ..............187
7.34 Address decode DIMM parameters. (MAD)—Offset 500Ch......................................188
7.35 Address decode DIMM parameters (MAD)—Offset 5010h .......................................190
7.36 MCDECS_CR_MRC_REVISION_0_0_0_MCHBAR_MCMAIN—Offset 5034h..................191
7.37 Request count from GT (DRAM)—Offset 5040h ....................................................191
7.38 Request count from IA (DRAM)—Offset 5044h .....................................................192
7.39 Request count from IO (DRAM)—Offset 5048h .....................................................193
7.40 RD data count (DRAM)—Offset 5050h.................................................................193
7.41 WR data count (DRAM)—Offset 5054h ................................................................194
7.42 Self refresh configuration Register (PM)—Offset 5060h .........................................195
7.43 NCDECS_CR_GFXVTBAR_0_0_0_MCHBAR_NCU—Offset 5400h ..............................195
7.44 NCDECS_CR_VTDPVC0BAR_0_0_0_MCHBAR_NCU—Offset 5410h...........................196
7.45 PACKAGE—Offset 5820h ...................................................................................197
7.46 PKG—Offset 5828h ..........................................................................................199
7.47 PKG—Offset 5830h ..........................................................................................199
7.48 PKG—Offset 5838h ..........................................................................................200
7.49 PKG—Offset 5840h ..........................................................................................200