Specification Sheet

Datasheet, Volume 2 of 2 71
Host Bridge/DRAM Registers
3.15 Protected Audio Video Path Control (PAVPC)—
Offset 58h
All the bits in this register are locked by Intel TXT. When locked the R/W bits are RO.
Access Method
Default: 0h
2
1h
RW_L
D1F1EN:
0: Bus 0 Device 1 Function 1 is disabled and hidden.
1: Bus 0 Device 1 Function 1 is enabled and visible.
This bit will be set to 0b and remain 0b if:
- PEG11 capability is disabled by fuses, OR
- PEG11 is disabled by strap (PEG0CFGSEL)
1
1h
RW_L
D1F2EN:
0: Bus 0 Device 1 Function 2 is disabled and hidden.
1: Bus 0 Device 1 Function 2 is enabled and visible.
This bit will be set to 0b and remain 0b if:
- PEG12 capability is disabled by fuses, OR
- PEG12 is disabled by strap (PEG0CFGSEL)
0
1h
RO
D0EN: Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 58h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCMBASE
RSVD2
ASMFEN
RSVD1
OVTATTACK
HVYMODSEL
PAVPLCK
PAVPE
PCME
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RW_L
PCMBASE: Sizes supported in the processor: 1M, 2M, 4M and 8M. Base value
programmed (from Top of Stolen
Memory) itself defines the size of the WOPCM. Separate WOPCM size programming is
redundant information and not required. Default 1M size programming. 4M
recommended for the processor. This register is locked (becomes read-only) when
PAVPE = 1b.
19:7
0h
RW_L
RSVD2: These bits are reserved for future use.
6
0h
RW_L
ASMFEN: ASMF method enabled
0b Disabled (default).
1b Enabled.
This register is locked when PAVPLCK is set.