Specification Sheet

Host Bridge/DRAM Registers
70 Datasheet, Volume 2 of 2
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15
1h
RW_L
D8EN:
0: Bus 0 Device 8 is disabled and not visible.
1: Bus 0 Device 8 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 8 capability is disabled.
14
0h
RW
D7EN:
0: Bus 0 Device 7 is disabled and not visible.
1: Bus 0 Device 7 is enabled and visible.
Non-production BIOS code should provide a setup option to enable Bus 0 Device 7.
When enabled, Bus 0 Device 7 should be initialized in accordance to standard PCI
device initialization procedures.
13
0h
RW
D6EN: Reserved (RSVD)
12:11
0h
RO
Reserved (RSVD): Reserved.
10
1h
RW_L
D5EN:
0: Bus 0 Device 5 is disabled and not visible.
1: Bus 0 Device 5 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 5 capability is disabled.
9:8
0h
RO
Reserved (RSVD): Reserved.
7
1h
RW_L
D4EN:
0: Bus 0 Device 4 is disabled and not visible.
1: Bus 0 Device 4 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 4 capability is disabled.
6
0h
RO
Reserved (RSVD): Reserved.
5
1h
RW_L
D3EN:
0: Bus 0 Device 3 is disabled and hidden
1: Bus 0 Device 3 is enabled and visible
This bit will be set to 0b and remain 0b if Device 3 capability is disabled.
4
1h
RW_L
D2EN:
0: Bus 0 Device 2 is disabled and hidden
1: Bus 0 Device 2 is enabled and visible
This bit will be set to 0b and remain 0b if Device 2 capability is disabled.
3
1h
RW_L
D1F0EN:
0: Bus 0 Device 1 Function 0 is disabled and hidden.
1: Bus 0 Device 1 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG10 capability is disabled.