Specification Sheet
Datasheet, Volume 2 of 2 69
Host Bridge/DRAM Registers
3.14 Device Enable (DEVEN)—Offset 54h
Allows for enabling/disabling of PCI devices and functions that are within the Processor
package. The table below the bit definitions describes the behavior of all combinations
of transactions to devices controlled by this register.
All the bits in this register are Intel TXT Lockable.
Access Method
Default: 84BFh
5:3
0h
RO
Reserved (RSVD): Reserved.
2
0h
RW_L
VAMEN: Enables the use of the iGFX engines for Versatile Acceleration.
1: iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 048000h.
0:- iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h.
1
0h
RW_L
IVD:
0: Enable. Device 2 (Processor Graphics) claims VGA memory and IO cycles, the Sub-
Class Code within Device 2 Class Code register is 00.
1: Disable. Device 2 (Processor Graphics) does not claim VGA cycles (Mem and IO),
and the Sub- Class Code field within Device 2 function 0 Class Code register is 80.
BIOS Requirement: BIOS should not set this bit to 0 if the GMS field (bits 7:3 of this
register) pre-allocates no memory.
This bit should be set to 1 if Device 2 is disabled either via a fuse or fuse override
(CAPID0_A[Processor Graphics] = 1) or via a register (DEVEN[3] = 0).
This register is locked by Intel TXT lock.
0
0h
RW_KL
GGCLCK: When set to 1b, this bit will lock all bits in this register.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 54h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
RSVD
D8EN
D7EN
D6EN
RSVD
D5EN
RSVD
D4EN
RSVD
D3EN
D2EN
D1F0EN
D1F1EN
D1F2EN
D0EN