Specification Sheet

Host Bridge/DRAM Registers
68 Datasheet, Volume 2 of 2
3.13 GMCH Graphics Control Register (GGC)—Offset
50h
All the bits in this register are Intel TXT lockable.
Access Method
Default: 500h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:15
0h
RW
MCHBAR: This field corresponds to bits 38 to 15 of the base address Host Memory
Mapped configuration space. BIOS will program this register resulting in a base
address for a 32KB block of contiguous memory address space. This register ensures
that a naturally aligned 32KB space is allocated within the first 512GB of addressable
memory space. System Software uses this base address to program the Host Memory
Mapped register set. All the bits in this register are locked in Intel TXT mode.
14:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW
MCHBAREN: 0: MCHBAR is disabled and does not claim any memory
1: MCHBAR memory mapped accesses are claimed and decoded appropriately
This register is locked in Intel TXT mode.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:0, F:0] + 50h
15 12 8 4 0
0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
GMS
GGMS
RSVD
VAMEN
IVD
GGCLCK
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
5h
RW_L
GMS: This field is used to select the amount of Main Memory that is pre-allocated to
support the Processor Graphics device in VGA (non-linear) and Native (linear) modes.
The BIOS ensures that memory is pre-allocated only when Processor Graphics is
enabled.
This register is also Intel TXT lockable.
Hardware does not clear or set any of these bits automatically based on Processor
Graphics being disabled/enabled.
BIOS Requirement: BIOS should not set this field to 0h if IVD (bit 1 of this register)
is 0.
7:6
0h
RW_L
GGMS: This field is used to select the amount of Main Memory that is pre-allocated to
support the Processor Graphics Translation Table. The BIOS ensures that memory is
pre-allocated only when Processor Graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS needs
to allocate a contiguous memory chunk. Hardware will derive the base of GSM from
DSM only using the GSM size programmed in the register.
Hardware functionality in case of programming this value to Reserved is not
guaranteed.