Specification Sheet
Datasheet, Volume 2 of 2 67
Host Bridge/DRAM Registers
3.12 Host Memory Mapped Register Range Base
(MCHBAR)—Offset 48h
This is the base address for the Host Memory Mapped Configuration space. There is no
physical memory within this 32KB window that can be addressed. The 32KB reserved
by this register does not alias to any PCI 2.3 compliant memory mapped space. On
reset, the Host MMIO Memory Mapped Configuration space is disabled and should be
enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
All the bits in this register are locked in Intel TXT mode.
The register space contains memory control, initialization, timing, and buffer strength
registers; clocking registers; and power and thermal management registers.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW
PXPEPBAR: This field corresponds to bits 38 to 12 of the base address PCI Express
Egress Port MMIO configuration space. BIOS will program this register resulting in a
base address for a 4KB block of contiguous memory address space. This register
ensures that a naturally aligned 4KB space is allocated within the first 512GB of
addressable memory space. System Software uses this base address to program the
PCI Express Egress Port MMIO register set. All the bits in this register are locked in
Intel TXT mode.
11:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW
PXPEPBAREN: 0: PXPEPBAR is disabled and does not claim any memory
1: PXPEPBAR memory mapped accesses are claimed and decoded appropriately
This register is locked by Intel TXT.
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 48h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
MCHBAR
RSVD
MCHBAREN