Specification Sheet
Host Bridge/DRAM Registers
66 Datasheet, Volume 2 of 2
3.10 Capabilities Pointer (CAPPTR)—Offset 34h
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Access Method
Default: E0h
3.11 PCI Express* Egress Port Base Address
(PXPEPBAR)—Offset 40h
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4KB window that can be addressed. The 4KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and should be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
All the bits in this register are locked in Intel TXT mode.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:0, F:0] + 34h
7 4 0
1 1 1 0 0 0 0 0
CAPPTR
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
E0h
RO
CAPPTR: Capabilities Pointer: Pointer to the offset of the first capability ID register
block. In this case the first capability is the product-specific Capability Identifier
(CAPID0).
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 40h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
PXPEPBAR
RSVD
PXPEPBAREN