Specification Sheet

Datasheet, Volume 2 of 2 545
GTTMMADR Registers
29
0h
RO
SFL: This field is valid only for implementations supporting advanced fault logging.
Software sets this field to request hardware to set/update the fault-log pointer used by
hardware. The fault-log pointer is specified through Advanced Fault Log register.
Hardware reports the status of the 'Set Fault Log' operation through the FLS field in
the Global Status register.
The fault log pointer should be set before enabling advanced fault logging (through
EAFL field). Once advanced fault logging is enabled, the fault log pointer may be
updated through this field while DMA remapping is active.
Clearing this bit has no effect. The value returned on read of this field is undefined.
28
0h
RO
EAFL: This field is valid only for implementations supporting advanced fault logging.
Software writes to this field to request hardware to enable or disable advanced fault
logging:
0: Disable advanced fault logging. In this case, translation faults are reported through
the Fault Recording registers.
1: Enable use of memory-resident fault log. When enabled, translation faults are
recorded in the memory-resident log. The fault log pointer should be set in hardware
(through the SFL field) before enabling advanced fault logging. Hardware reports the
status of the advanced fault logging enable operation through the AFLS field in the
Global Status register.
The value returned on read of this field is undefined.
27
0h
RO
WBF: This bit is valid only for implementations requiring write buffer flushing.
Software sets this field to request that hardware flush the Root-Complex internal write
buffers. This is done to ensure any updates to the memory-resident remapping
structures are not held in any internal write posting buffers.
Hardware reports the status of the write buffer flushing operation through the WBFS
field in the Global Status register.
Clearing this bit has no effect. The value returned on a read of this field is undefined.
26
0h
RO_V
QIE: This field is valid only for implementations supporting queued invalidations.
Software writes to this field to enable or disable queued invalidations.
0: Disable queued invalidations.
1: Enable use of queued invalidations.
Hardware reports the status of queued invalidation enable operation through QIES
field in the Global Status register.
The value returned on a read of this field is undefined.
25
0h
RO_V
IRE: This field is valid only for implementations supporting interrupt remapping.
0: Disable interrupt-remapping hardware
1: Enable interrupt-remapping hardware
Hardware reports the status of the interrupt remapping enable operation through the
IRES field in the Global Status register.
There may be active interrupt requests in the platform when software updates this
field. Hardware should enable or disable interrupt-remapping logic only at
deterministic transaction boundaries, so that any in-flight interrupts are either subject
to remapping or not at all.
Hardware implementations should drain any in-flight interrupts requests queued in the
Root-Complex before completing the interrupt-remapping enable command and
reflecting the status of the command through the IRES field in the Global Status
register.
The value returned on a read of this field is undefined.
Bit
Range
Default &
Access
Field Name (ID): Description