Specification Sheet
GTTMMADR Registers
540 Datasheet, Volume 2 of 2
15.8 Protected High-Memory Base Register
(MPHMBASE)—Offset 108240h
Register to set up the base address of DMA-protected high-memory region. This
register should be set up before enabling protected memory through PMEN_REG, and
should not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as Clear in the Capability register).
The alignment of the protected high memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1's to this
register, and finding most significant zero bit position below host address width (HAW)
in the value read back from the register. Bits N:0 of this register are decoded by
hardware as all 0s.
Software may setup the protected high memory region either above or below 4GB.
Software should not modify this register when protected memory regions are enabled
(PRS field Set in PMEN_REG).
Access Method
Default: 0h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLML
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RO_V
PLML: This register specifies the last host physical address of the DMA-protected low-
memory region in system memory.
19:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:2, F:0] + 108240h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
PHMB
RSVD