Specification Sheet

Datasheet, Volume 2 of 2 537
GTTMMADR Registers
15.5 Protected Memory Enable Register (MPMEN)—
Offset 108180h
Register to enable the DMA-protected memory regions setup through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for
implementations not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).
Protected memory regions may be used by software to securely initialize remapping
structures in memory. To avoid impact to legacy BIOS usage of memory, software is
recommended to not overlap protected memory regions with any reserved memory
regions of the platform reported through the Reserved Memory Region Reporting
(RMRR) structures.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
1h
RO_V
BGSM: This register contains the base address of stolen DRAM memory for the GTT.
BIOS determines the base of GTT stolen memory by subtracting the GTT graphics
stolen memory size (PCI Device 0 offset 50 bits 7:6) from the Graphics Base of Data
Stolen Memory (PCI Device 0 offset B0 bits 31:20).
19:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RO_V
LOCK: This bit will lock all writeable settings in this register, including itself.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:2, F:0] + 108180h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPM
RSVD
PRS