Specification Sheet

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Datasheet, Volume 2 of 2 533

GTTMMADR Registers

15 GTTMMADR Registers

15.1 Top of Low Usable DRAM (MTOLUD)—Offset

108000h

This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory

and Graphics Stolen Memory are within the DRAM space defined. From the top, the

Host optionally claims 1 to 64MBs of DRAM for Processor Graphics if enabled, 1or 2MB

of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for

TSEG if enabled.

Programming Example:

C1DRB3 is set to 4GB

TSEG is enabled and TSEG size is set to 1MB

Processor Graphics is enabled, and Graphics Mode Select is set to 32MB

GTT Graphics Stolen Memory Size set to 2MB

BIOS knows the OS requires 1G of PCI space.

BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by

the system. This 20MB range at the very top of addressable memory space is lost to

APIC and Intel TXT.

According to the above equation, TOLUD is originally calculated to: 4GB =

1_0000_0000h

The system memory requirements are: 4GB (max addressable space) - 1GB (pci

space) - 35MB (lost memory) = 3GB - 35MB (minimum granularity) = 0_ECB0_0000h

Since 0_ECB0_0000h (PCI and other system requirements) is less than

1_0000_0000h, TOLUD should be programmed to ECBh.

These bits are Intel TXT lockable.

Table 15-1. Summary of Bus: 0, Device: 2, Function: 0 (MEM)

Offset

Size

(Bytes)

108000–108003h 4 Top of Low Usable DRAM (MTOLUD)—Offset 108000h 100000h

108080–108087h 8 Top of Upper Usable DRAM (MTOUUD)—Offset 108080h 0h

1080C0–1080C3h 4 Base Data of Stolen Memory (MBDSM)—Offset 1080C0h 0h

108100–108103h 4 Base of GTT stolen Memory (MBGSM)—Offset 108100h 100000h

108180–108183h 4 Protected Memory Enable Register (MPMEN)—Offset 108180h 0h

1081C0–1081C3h 4 Protected Low-Memory Base Register (MPLMBASE)—Offset 1081C0h 0h

108200–108203h 4 Protected Low-Memory Limit Register (MPLMLIMIT)—Offset 108200h 0h

108240–108247h 8 Protected High-Memory Base Register (MPHMBASE)—Offset 108240h 0h

108280–108287h 8 Protected High-Memory Limit Register (MPHMLIMIT)—Offset 108280h 0h

1082C0–1082C3h 4 Protected Audio Video Path Control (MPAVPC)—Offset 1082C0h 0h

108300–108303h 4 Global Command Register (MGCMD)—Offset 108300h 0h