Specification Sheet

PCI Express* Controller (x4) Registers
532 Datasheet, Volume 2 of 2
14.64 PEG Root Error Status—Offset 1F0h
The Root Error Status register reports status of error messages received by the root
complex, and of errors detected by the Root Port itself (which are treated conceptually
as if the Root Port had sent an error message to itself). This register is updated
regardless of the settings of the Root Control register and the Root Error Command
register (which is not even implemented).
When an error is received by the Root Complex, the respective error received bit is set
which indicates that a particular error category occurred. Software may clear an error
status by writing a 1 to the respective bit.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1F0h
(Size: 32 bits)
Default: 0h
14.65 PEG Error Source Identification—Offset 1F4h
The PCI Express Advanced Error Reporting (AER) register the requester ID of the first
PCIE Correctable and Uncorrectable (Fatal/Non-Fatal) errors.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1F4h
(Size: 32 bits)
Default: 0h
§ §
Bit
Range
Default &
Access
Field Name (ID): Description
31:27 0h RO AEIMN: Reserved for Advanced Error Interrupt Message Number:
26:7 0h RW1CS Reserved (RSVD): Reserved.
6 0h RW1CS FEMR: Fatal Error Messages Received:
5 0h RW1CS NFEMR: Non-Fatal Error Messages Received:
4 0h RW1CS FUF: First Uncorrectable Fatal:
3 0h RW1CS MEFNR: Multiple ERR_FATAL/NONFATAL Received:
2 0h RW1CS EFNFR: ERR_FATAL/NONFATAL Received: Set when either a fatal or a non-fatal
error message is received and this bit is not already set.
1 0h RW1CS MECR: Multiple ERR_COR Received:
0 0h RW1CS ECR: ERR_COR Received: Set when a correctable error message is received and
this bit is not already set.
Bit
Range
Default &
Access
Field Name (ID): Description
31:16 0h ROS EFNSI: Error Fatal/Non-Fatal Source Identification
15:0 0h ROS ECSI: Error Correctable Source Identification