Specification Sheet

Datasheet, Volume 2 of 2 531
PCI Express* Controller (x4) Registers
14.62 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h
The PCI Express Advanced Error Reporting (AER) capability for header logging will use
this register for a header log.
Note: This description refers to all Header Log registers (HL0-HL3).
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1DCh/1E0h/1E4h/1E8h
(Size: 32 bits)
Default: 0h
14.63 PEG Root Error Command—Offset 1ECh
The Root Error Command register allows further control of Root Complex response to
Correctable, Non-Fatal, and Fatal error Messages. Bit fields enable or disable generation
of interrupts in addition to Do_SERR VDM sent to PCH.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1ECh
(Size: 32 bits)
Default: 0h
8 0h RO ECRCCE: ECRC Check Enable
7 0h RO ECRCCC: ECRC Check Capable
6 0h RO ECRCGE: ECRC Generation Enable
5 0h R0 ECRCGC: ECRC Generation Capable
4:0 0h ROS FEP: First Error Pointer
Bit
Range
Default &
Access
Field Name (ID): Description
Bit
Range
Default &
Access
Field Name (ID): Description
31:0 0h ROS HTAE: Header of TLP Associated with Error
Bit
Range
Default &
Access
Field Name (ID): Description
31:3 0h RW Reserved (RSVD): Reserved.
2 0h RW FERE:
Fatal Error Reporting Enable
1 0h RW NFERE: Non-Fatal Error Reporting Enable
0 0h RW CERE: Correctable Error Reporting Enable