Specification Sheet

PCI Express* Controller (x4) Registers
530 Datasheet, Volume 2 of 2
14.60 PEG Correctable Error Mask—Offset 1D4h
Controls reporting of individual correctable errors by the device (or logic associated
with this port) to the PCI Express Root Complex. As these errors are not originating on
the other side of a PCI Express link, no PCI Express error message is sent, but the
unmasked error is reported directly to the root control logic. A masked error
(respective bit set to 1 in the mask register) has no action taken. There is a mask bit
per error bit of the Correctable Error Status register. This register is for test and debug
purposes only.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1D4h
(Size: 32 bits)
Default: 0h
14.61 PEG Advanced Error Capabilities and Control—
Offset 1D8h
The PCI Express Advanced Error Reporting (AER) capabilities defined through this
register. First Error is logged here.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1D8h
(Size: 32 bits)
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:14 0h RWS Reserved (RSVD): Reserved.
13 0h RWS ANFEM:
Advisory Non-Fatal Error Mask: Advisory Non-Fatal Error Mask
(ANFEM): When set, masks Advisory Non-Fatal errors from:
a. signaling ERR_COR to the device control register, and
a. updating the Uncorrectable Error Status register.
This register is set by default to enable compatibility with software that does
not comprehend Role-Based Error Reporting.
12 0h RWS RTTM: Replay Timer Timeout
Mask
11:9 0h RWS Reserved (RSVD): Reserved.
8 0h RWS RNRM: Replay Number Rollover Mask
7 0h RWS BDLLPM: Bad DLLP Mask
6 0h RWS BTLPM: Bad TLP Mask
5:1 0h RWS Reserved (RSVD): Reserved.
0 0h RWS REM: Receiver Error Mask
Bit
Range
Default &
Access
Field Name (ID): Description
31:11 0h RO Reserved (RSVD): Reserved.
10 0h RO MHRE: Multiple Header Recording Enable
9 0h RO MHRC: Multiple Header Recording Capable