Specification Sheet

PCI Express* Controller (x4) Registers
528 Datasheet, Volume 2 of 2
14.57 PEG Uncorrectable Error Mask—Offset 1C8h
Controls reporting of individual errors by the device (or logic associated with this port)
to the PCI Express Root Complex. As these errors are not originating on the other side
of a PCI Express link, no PCI Express error message is sent, but the unmasked error is
reported directly to the root control logic. A masked error (respective bit set to 1 in the
mask register) has no action taken. There is a mask bit per error bit of the
Uncorrectable Error Status register. This register is for test and debug purposes only.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1C8h
(Size: 32 bits)
Default: 0h
14.58 PEG Uncorrectable Error Severity—Offset 1CCh
Controls whether an individual error is reported as a non-fatal or fatal error. An error is
reported as fatal when the corresponding error bit in the severity register is set. If the
bit is cleared, the corresponding error is considered nonfatal. This register is for test
and debug purposes only.
Access Method
Type: CFG Offset: [B:0, D:1, F:2] + 1CCh
(Size: 32 bits)
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:21 0h RWS Reserved (RSVD): Reserved.
20 0h RWS UREM:
Unsupported Request Error Mask
19 0h RO ECRCEM: Reserved for ECRC Error Mask
18 0h RWS MTLPM: Malformed TLP Mask
17 0h RWS ROM: Receiver Overflow Mask
16 0h RWS UCM: Unexpected Completion Mask
15 0h RO CAM: Reserved for Completer Abort Mask
14 0h RWS CTM: Completion Timeout Mask
13 0h RO FCPEM: Reserved for Flow Control Protocol Error Mask
12 0h RWS PTLPM: Poisoned TLP Mask
11:5 0h RWS Reserved (RSVD): Reserved.
4 0h RWS DLPEM: Data Link Protocol Error Mask
3:0 0h RWS Reserved (RSVD): Reserved.