Specification Sheet
Host Bridge/DRAM Registers
62 Datasheet, Volume 2 of 2
15 12 8 4 0
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
DPE
SSE
RMAS
RTAS
STAS
DEVT
DPD
FB2B
RSVD
MC66
CLIST
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RW1C
DPE: Detected Parity Error: This bit is set when this Device receives a Poisoned TLP.
14
0h
RW1C
SSE: Signaled System Error: This bit is set to 1 when Device 0 generates an SERR
message over DMI for any enabled Device 0 error condition. Device 0 error conditions
are enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device 0 error flags
are read/reset from the PCISTS, ERRSTS, or DMIUEST registers. Software clears this
bit by writing a 1 to it.
13
0h
RW1C
RMAS: Received Master Abort Status: This bit is set when the Processor generates a
DMI request that receives an Unsupported Request completion packet. Software clears
this bit by writing a 1 to it.
12
0h
RW1C
RTAS: Received Target Abort Status: This bit is set when the Processor generates a
DMI request that receives a Completer Abort completion packet. Software clears this
bit by writing a 1 to it.
11
0h
RO
STAS: Signaled Target Abort Status: The Processor will not generate a Target Abort
DMI completion packet or Special Cycle. This bit is not implemented and is hardwired
to a 0. Writes to this bit position have no effect.
10:9
0h
RO
DEVT: DEVSEL Timing: These bits are hardwired to "00". Writes to these bit positions
have no affect. Device 0 does not physically connect to PCI_A. These bits are set to
"00" (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by the
Host.
8
0h
RW1C
DPD: Master Data Parity Error Detected: This bit is set when DMI received a Poisoned
completion from PCH.
This bit can only be set when the Parity Error Enable bit in the PCI Command register
is set.
7
1h
RO
FB2B: Fast Back-to-Back: This bit is hardwired to 1. Writes to these bit positions have
no effect. Device 0 does not physically connect to PCI_A. This bit is set to 1 (indicating
fast back-to-back capability) so that the optimum setting for PCI_A is not limited by
the Host.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
MC66: 66 MHz Capable: Does not apply to PCI Express. should be hardwired to 0.
4
1h
RO
CLIST: Capability List: This bit is hardwired to 1 to indicate to the configuration
software that this device/function implements a list of new capabilities. A list of new
capabilities is accessed via register CAPPTR at configuration address offset 34h.
Register CAPPTR contains an offset pointing to the start address within configuration
space of this device where the Capability Identification register resides.
3:0
0h
RO
Reserved (RSVD): Reserved.