Specification Sheet

Datasheet, Volume 2 of 2 5
4.11 Graphics Memory Range Address (GMADR)—Offset 18h..........................................97
4.12 I/O Base Address (IOBAR)—Offset 20h................................................................. 98
4.13 Subsystem Vendor Identification (SVID2)—Offset 2Ch............................................ 99
4.14 Subsystem Identification (SID2)—Offset 2Eh....................................................... 100
4.15 Video BIOS ROM Base Address (ROMADR)—Offset 30h ......................................... 100
4.16 Capabilities Pointer (CAPPOINT)—Offset 34h ....................................................... 101
4.17 Interrupt Line (INTRLINE)—Offset 3Ch ............................................................... 101
4.18 Interrupt Pin (INTRPIN)—Offset 3Dh .................................................................. 102
4.19 Minimum Grant (MINGNT)—Offset 3Eh ............................................................... 103
4.20 Maximum Latency (MAXLAT)—Offset 3Fh............................................................ 103
4.21 Capabilities A (CAPID0)—Offset 44h................................................................... 104
4.22 Capabilities B (CAPID0)—Offset 48h................................................................... 105
4.23 Device Enable (DEVEN0)—Offset 54h ................................................................. 107
4.24 Base Data of Stolen Memory (BDSM)—Offset 5Ch ................................................ 108
4.25 Multi Size Aperture Control (MSAC)—Offset 62h .................................................. 109
4.26 PCI Express Capability Header (PCIECAPHDR)—Offset 70h .................................... 111
4.27 Message Signaled Interrupts Capability ID (MSI)—Offset ACh................................ 111
4.28 Message Control (MC)—Offset AEh..................................................................... 112
4.29 Message Address (MA)—Offset B0h.................................................................... 113
4.30 Message Data (MD)—Offset B4h ........................................................................ 113
4.31 Power Management Capabilities ID (PMCAPID)—Offset D0h .................................. 114
4.32 Power Management Capabilities (PMCAP)—Offset D2h .......................................... 115
4.33 Power Management Control/Status (PMCS)—Offset D4h ....................................... 116
5 Dynamic Power Performance Management (DPPM) Registers................................ 117
5.1 Device Enable (DEVEN)—Offset 54h................................................................... 117
5.2 Capabilities A (CAPID0)—Offset E4h................................................................... 118
5.3 Capabilities B (CAPID0)—Offset E8h................................................................... 120
6 DMIBAR Registers ................................................................................................. 122
6.1 DMI Virtual Channel Enhanced Capability (DMIVCECH)—Offset 0h.......................... 123
6.2 DMI Port VC Capability Register 1 (DMIPVCCAP1)—Offset 4h................................. 123
6.3 DMI Port VC Capability Register 2 (DMIPVCCAP2)—Offset 8h................................. 124
6.4 DMI Port VC Control (DMIPVCCTL)—Offset Ch ..................................................... 125
6.5 DMI VC0 Resource Capability (DMIVC0RCAP)—Offset 10h ..................................... 126
6.6 DMI VC0 Resource Control (DMIVC0RCTL)—Offset 14h ......................................... 127
6.7 DMI VC0 Resource Status (DMIVC0RSTS)—Offset 1Ah.......................................... 128
6.8 DMI VC1 Resource Capability (DMIVC1RCAP)—Offset 1Ch..................................... 129
6.9 DMI VC1 Resource Control (DMIVC1RCTL)—Offset 20h ......................................... 130
6.10 DMI VC1 Resource Status (DMIVC1RSTS)—Offset 26h.......................................... 131
6.11 DMI VCm Resource Capability (DMIVCMRCAP)—Offset 34h ................................... 132
6.12 DMI VCm Resource Control (DMIVCMRCTL)—Offset 38h ....................................... 133
6.13 DMI VCm Resource Status (DMIVCMRSTS)—Offset 3Eh ........................................ 134
6.14 DMI Root Complex Link Declaration (DMIRCLDECH)—Offset 40h ............................ 135
6.15 DMI Element Self Description (DMIESD)—Offset 44h ............................................ 136
6.16 DMI Link Entry 1 Description (DMILE1D)—Offset 50h ........................................... 137
6.17 DMI Link Entry 1 Address (DMILE1A)—Offset 58h ................................................ 138
6.18 DMI Link Upper Entry 1 Address (DMILUE1A)—Offset 5Ch..................................... 138
6.19 DMI Link Entry 2 Description (DMILE2D)—Offset 60h ........................................... 139
6.20 DMI Link Entry 2 Address (DMILE2A)—Offset 68h ................................................ 140
6.21 Link Capabilities (LCAP)—Offset 84h .................................................................. 140
6.22 Link Control (LCTL)—Offset 88h ........................................................................ 142
6.23 DMI Link Status (LSTS)—Offset 8Ah................................................................... 143
6.24 Link Control 2 (LCTL2)—Offset 98h .................................................................... 144
6.25 Link Status 2 (LSTS2)—Offset 9Ah..................................................................... 146
6.26 DMI Uncorrectable Error Status (DMIUESTS)—Offset 1C4h.................................... 147