Specification Sheet
Datasheet, Volume 2 of 2 523
PCI Express* Controller (x4) Registers
14.51 Port VC Capability Register 2 (PVCCAP2)—Offset
108h
Describes the configuration of PCI Express Virtual Channels associated with this port.
Access Method
Default: 0h
14.52 Port VC Control (PVCCTL)—Offset 10Ch
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 108h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VCATO
RSVD
VCAC
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RO
VCATO: VC Arbitration Table Offset: Indicates the location of the VC Arbitration Table.
This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the
base address of the Virtual Channel Capability Structure. A value of 0 indicates that
the table is not present (due to fixed VC priority).
23:8
0h
RO
Reserved (RSVD): Reserved.
7:0
0h
RO
VCAC: Reserved for VC Arbitration Capability:
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + 10Ch
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
VCAS
VCARB