Specification Sheet

PCI Express* Controller (x4) Registers
522 Datasheet, Volume 2 of 2
14.50 Port VC Capability Register 1 (PVCCAP1)—Offset
104h
Describes the configuration of PCI Express Virtual Channels associated with this port.
Access Method
Default: 0h
2
0h
ROV
EQPH1SUCC: Equalization Phase 1 Successful When set to 1b, this bit
indicates that Phase 1 of the Transmitter Equalization procedure
has successfully completed.
1
0h
ROV
EQCOMPLETE: Equalization Complete When set to 1b, this bit indicates that
the Transmitter Equalization procedure has completed.
0
0h
RO
CURDELVL: Current De-emphasis Level: Current De-emphasis Level - When the Link
is operating at 5 GT/s speed, this reflects the level of de-emphasis.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:2] + 104h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
LPEVCC
RSVD
EVCC
Bit
Range
Default &
Access
Field Name (ID): Description
31:7
0h
RO
Reserved (RSVD): Reserved.
6:4
0h
RO
LPEVCC: Low Priority Extended VC Count: Indicates the number of (extended) Virtual
Channels in addition to the default VC belonging to the low-priority VC (LPVC) group
that has the lowest priority with respect to other VC resources in a strict-priority VC
Arbitration.
The value of 0 in this field implies strict VC arbitration.
3
0h
RO
Reserved (RSVD): Reserved.
2:0
0h
RO
EVCC: Extended VC Count: Indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.