Specification Sheet

PCI Express* Controller (x4) Registers
518 Datasheet, Volume 2 of 2
14.47 Device Control 2 (DCTL2)—Offset C8h
Access Method
Default: 0h
5
0h
RO
ARIFS: ARI Forwarding Supported: Applicable only to Switch Downstream Ports and
Root Ports; should be 0b for other Function types. This bit should be set to 1b if a
Switch Downstream Port or Root Port supports this optional capability.
4
0h
RO
CTODS: Completion Timeout Disabled Supported: A value of 1b indicates support for
the Completion Timeout Disable mechanism.
The Completion Timeout Disable mechanism is required for Endpoints that issue
Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take
ownership of Requests issued on PCI Express.
This mechanism is optional for Root Ports. The Root port does nopt support completion
timeout disable
3:0
0h
RO
CTOR: Completion Timer Ranges Supported: device Function support for the optional
Completion Timeout programmability mechanism. This mechanism allows system
software to modify the Completion Timeout value.
This field is applicable only to Root Ports, Endpoints that issue Requests on their own
behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued
on PCI Express. For all other Functions this field is reserved and should be hardwired
to 0000b.
0000b Completion Timeout programming not supported - the Function should
implement a timeout value in the range 50 us to 50 ms.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + C8h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
OBFFEN
RSVD
LTREN
RSVD
ATOMIC_OP_REQUESTER_EN
ARIFEN
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
Reserved (RSVD): Reserved.
14:13
0h
RW
OBFFEN: Reserved.
12:11
0h
RO
Reserved (RSVD): Reserved.