Specification Sheet

Datasheet, Volume 2 of 2 61
Host Bridge/DRAM Registers
3.4 PCI Status (PCISTS)—Offset 6h
This status register reports the occurrence of error events on Device 0's PCI interface.
Since Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Access Method
Default: 90h
Bit
Range
Default &
Access
Field Name (ID): Description
15:10
0h
RO
Reserved (RSVD): Reserved.
9
0h
RO
FB2B: Fast Back-to-Back Enable: This bit controls whether or not the master can do
fast back-to-back write. Since device 0 is strictly a target this bit is not implemented
and is hardwired to 0. Writes to this bit position have no effect.
8
0h
RW
SERRE: SERR Enable: This bit is a global enable bit for Device 0 SERR messaging. The
Processor communicates the SERR condition by sending an SERR message over DMI to
the PCH.
1: The Processor is enabled to generate SERR messages over DMI for specific Device
0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK
registers. The error status is reported in the ERRSTS, PCISTS, and DMIUEST registers.
0: The SERR message is not generated by the Host for Device 0.
This bit only controls SERR messaging for Device 0. Other integrated devices have
their own SERRE bits to control error reporting for error conditions occurring in each
device. The control bits are used in a logical OR manner to enable the SERR DMI
message mechanism.
OPI N/A
7
0h
RO
ADSTEP: Address/Data Stepping Enable: Address/data stepping is not implemented
in the CPU, and this bit is hardwired to 0. Writes to this bit position have no effect.
6
0h
RW
PERRE: OPI - N/A Parity Error Enable: Controls whether or not the Master Data Parity
Error bit in the PCI Status register can bet set.
0: Master Data Parity Error bit in PCI Status register can NOT be set.
1: Master Data Parity Error bit in PCI Status register CAN be set.
5
0h
RO
VGASNOOP: VGA Palette Snoop Enable: The Processor does not implement this bit
and it is hardwired to a 0. Writes to this bit position have no effect.
4
0h
RO
MWIE: Memory Write and Invalidate Enable: The Processor will never issue memory
write and invalidate commands. This bit is therefore hardwired to 0. Writes to this bit
position will have no effect.
3
0h
RO
SCE: Special Cycle Enable: The Processor does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
2
1h
RO
BME: Bus Master Enable: The Processor is always enabled as a master on the
backbone. This bit is hardwired to a "1". Writes to this bit position have no effect.
1
1h
RO
MAE: Memory Access Enable: The Processor always allows access to main memory,
except when such access would violate security principles. Such exceptions are
outside the scope of PCI control. This bit is not implemented and is hardwired to 1.
Writes to this bit position have no effect.
0
0h
RO
IOAE: I/O Access Enable: This bit is not implemented in the Processor and is
hardwired to a 0. Writes to this bit position have no effect.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:0, F:0] + 6h