Specification Sheet

Datasheet, Volume 2 of 2 513
PCI Express* Controller (x4) Registers
14.43 Slot Status (SLOTSTS)—Offset BAh
PCI Express Slot related registers.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + BAh
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DLLSC
EIS
PDS
MSS
CC
PDC
MSC
PFD
ABP
Bit
Range
Default &
Access
Field Name (ID): Description
15:9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RO
DLLSC: Reserved for Data Link Layer State Changed: This bit is set when the value
reported in the Data Link Layer Link Active field of the Link Status register is changed.
In response to a Data Link Layer State Changed event, software should read the Data
Link Layer Link Active field of the Link Status register to determine if the link is active
before initiating configuration cycles to the hot plugged device.
7
0h
RO
EIS: Reserved for Electromechanical Interlock Status: If an Electromechanical
Interlock is implemented, this bit indicates the current status of the Electromechanical
Interlock.
Defined encodings are:
0: Electromechanical Interlock Disengaged
1: Electromechanical Interlock Engaged
6
0h
ROV
PDS: Presence Detect State: --In band presence detect state:
0: Slot Empty
1: Card present in slot
This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of
the Physical Layer in-band presence detect mechanism and, if present, any out-of-
band presence detect mechanism defined for the slot's corresponding form factor.
Note that the in-band presence detect mechanism requires that power be applied to
an adapter for its presence to be detected. Consequently, form factors that require a
power controller for hot-plug should implement a physical pin presence detect
mechanism.
Defined encodings are:
0: Slot Empty
1: Card Present in slot
This register should be implemented on all Downstream Ports that implement slots.
For Downstream Ports not connected to slots (where the Slot Implemented bit of the
PCI Express Capabilities Register is 0b), this bit should return 1b.
5
0h
RO
MSS: Reserved for MRL Sensor State: This register reports the status of the MRL
sensor if it is implemented.
Defined encodings are:
0: MRL Closed
1: MRL Open