Specification Sheet

Datasheet, Volume 2 of 2 507
PCI Express* Controller (x4) Registers
14.39 Link Control (LCTL)—Offset B0h
Allows control of PCI Express link.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + B0h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
LABIE
LBMIE
HAWD
ECPM
ES
CCC
RL LD
RCB
RSVD
ASPM
Bit
Range
Default &
Access
Field Name (ID): Description
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0h
RW
LABIE: Link Autonomous Bandwidth Interrupt Enable: Link Autonomous Bandwidth
Interrupt Enable - When Set, this bit enables the generation of an interrupt to indicate
that the Link Autonomous Bandwidth Status bit has been Set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to PCI/PCI-
X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability should
hardwire this bit to 0b.
10
0h
RW
LBMIE: Link Bandwidth Management Interrupt Enable: Link Bandwidth Management
Interrupt Enable - When Set, this bit enables the generation of an interrupt to indicate
that the Link Bandwidth Management Status bit has been Set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to PCI/PCI-
X bridges, and Upstream Ports of Switches.
9
0h
RO
HAWD: Hardware Autonomous Width Disable: Hardware Autonomous Width Disable -
When Set, this bit disables hardware from changing the Link width for reasons other
than attempting to correct unreliable Link operation by reducing Link width.
Devices that do not implement the ability autonomously to change Link width are
permitted to hardwire this bit to 0b.
8
0h
RO
ECPM: Enable Clock Power Management: Applicable only for form factors that support
a "Clock Request" (CLKREQ#) mechanism, this enable functions as follows
0: Clock power management is disabled and device should hold CLKREQ# signal low
1: When this bit is set to 1 the device is permitted to use CLKREQ# signal to power
manage link clock according to protocol defined in appropriate form factor
specification.
Default value of this field is 0b.
Components that do not support Clock Power Management (as indicated by a 0b value
in the Clock Power Management bit of the Link Capabilities Register) should hardwire
this bit to 0b.
7
0h
RW
ES: Extended Synch: Extended synch
0: Standard Fast Training Sequence (FTS).
1: Forces the transmission of additional ordered sets when exiting the L0s state and
when in the Recovery state.
This mode provides external devices (e.g., logic analyzers) monitoring the Link time to
achieve bit and symbol lock before the link enters L0 and resumes communication.
This is a test mode only and may cause other undesired side effects such as buffer
overflows or underruns.