Specification Sheet

Datasheet, Volume 2 of 2 501
PCI Express* Controller (x4) Registers
14.32 Message Data (MD)—Offset 98h
Access Method
Default: 0h
14.33 PCI Express-G Capability List (PEG)—Offset A0h
Enumerates the PCI Express capability structure.
Access Method
Default: 10h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + 98h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MD
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0h
RW
MD: Message Data: Base message data pattern assigned by system software and
used to handle an MSI from the device.
When the device should generate an interrupt request, it writes a 32-bit value to the
memory address specified in the MA register. The upper 16 bits are always set to 0.
The lower 16 bits are supplied by this register.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:2] + A0h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
PNC
CID
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
0h
RO
PNC: Pointer to Next Capability: This value terminates the capabilities list. The Virtual
Channel capability and any other PCI Express specific capabilities that are reported via
this mechanism are in a separate capabilities list located entirely within PCI Express
Extended Configuration Space.
7:0
10h
RO
CID: Capability ID: Identifies this linked list item (capability structure) as being for
PCI Express registers.